Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.

Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.

Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.

Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged.

Abstract: According to one embodiment, a layout verification apparatus includes a design section, a layout creation section, a first verification section and a second verification section. One of the first and second verification sections includes a filter processing section which executes a filter processing of a verification target element to be verified by a mask data used to a manufacture of the semiconductor integrated circuit, and the verification target element to be verified needs an ion implantation. The filter processing section comprises a first logic section which executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified.

Abstract: A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit which is independently erased, and the redundant block configured to replace the normal block and being incapable of replacing the special block. A defective block automatic replacement sequence control circuit controls the replacement operation of the defective block FBLK with the redundant block RBLK in a defective block automatic replacement sequence.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged.

Abstract: A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations of first memory cells and second memory cells, the bank decoder simultaneously selects the first and second banks, and first and second write load circuits simultaneously write data in memory cells in first and second blocks, respectively.

Abstract: A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit which is independently erased, and the redundant block configured to replace the normal block and being incapable of replacing the special block. A defective block automatic replacement sequence control circuit controls the replacement operation of the defective block FBLK with the redundant block RBLK in a defective block automatic replacement sequence.

Abstract: There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an even bit-stress test, the high voltage for write is supplied from the first load circuit for write to the even bit lines and a lower potential than the high voltage for write is supplied from the second load circuit for write to the odd bit lines. At the time of an odd bit-stress test, the lower potential is supplied from the first load circuit for write to the even bit lines and the high voltage for write is supplied from the second load circuit for write to the odd bit lines.

Abstract: A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations of first memory cells and second memory cells, the bank decoder simultaneously selects the first and second banks, and first and second write load circuits simultaneously write data in memory cells in first and second blocks, respectively.

Abstract: There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an even bit-stress test, the high voltage for write is supplied from the first load circuit for write to the even bit lines and a lower potential than the high voltage for write is supplied from the second load circuit for write to the odd bit lines. At the time of an odd bit-stress test, the lower potential is supplied from the first load circuit for write to the even bit lines and the high voltage for write is supplied from the second load circuit for write to the odd bit lines.

Abstract: A semiconductor device is disclosed, which comprises a voltage dividing resistor circuit including a plurality of resistor elements connected in series between a power supply node and a ground node, a voltage detecting PMOS transistor having a gate connected to an output node of the voltage dividing resistor circuit and a source connected to the power supply node, a resistor element connected between a drain of the voltage detecting PMOS transistor and a ground node, a CMOS inverter circuit supplied with a power supply voltage through the power supply node, having an input terminal connected to a drain of the voltage detecting PMOS transistor and an output terminal for outputting a power-on detection signal, and a monitoring pad which monitors a potential of the output node of the voltage dividing resistor circuit from exterior of a semiconductor chip.

Abstract: A semiconductor memory device includes a data line array connected to a memory cell array, a read circuit configured to charge selected data lines to read data, and a non-selection-side charge circuit configured to charge non-selected data lines. In the data line array, a first group of lower order 8 bit data lines and a second group of higher order 8 bit data lines are alternately disposed one line by one line. The read circuit selects and charges all the 16 bit data lines in a word data read mode, while it selects and charges one of the first and second groups in a byte data read mode. The non-selection-side charge circuit selects and charges non-selected data lines, which belong to the other of the first and second groups not selected by the read circuit in the byte data read mode.

Abstract: A semiconductor memory device includes a data line array connected to a memory cell array, a read circuit configured to charge selected data lines to read data, and a non-selection-side charge circuit configured to charge non-selected data lines. In the data line array, a first group of lower order 8 bit data lines and a second group of higher order 8 bit data lines are alternately disposed one line by one line. The read circuit selects and charges all the 16 bit data lines in a word data read mode, while it selects and charges one of the first and second groups in a byte data read mode. The non-selection-side charge circuit selects and charges non-selected data lines, which belong to the other of the first and second groups not selected by the read circuit in the byte data read mode.