Patents by Inventor Tomoji Nakamura
Tomoji Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11675005Abstract: The semiconductor device includes a transmitting-side hierarchical block, a receiving-side hierarchical block and an inter-block circuit. The transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit. The inter-block circuit transmits the output signal of the transmitting-side hierarchical block to the receiving-side hierarchical block.Type: GrantFiled: November 24, 2020Date of Patent: June 13, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masayuki Tsukuda, Tomoji Nakamura
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Publication number: 20220163584Abstract: The semiconductor device includes a transmitting-side hierarchical block, a receiving-side hierarchical block and an inter-block circuit. The transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit. The inter-block circuit transmits the output signal of the transmitting-side hierarchical block to the receiving-side hierarchical block.Type: ApplicationFiled: November 24, 2020Publication date: May 26, 2022Inventors: Masayuki TSUKUDA, Tomoji NAKAMURA
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Patent number: 9291671Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).Type: GrantFiled: November 19, 2013Date of Patent: March 22, 2016Assignee: Hitachi, Ltd.Inventors: Yasuyoshi Sunaga, Hideki Sakakibara, Yuko Ito, Tomoji Nakamura, Atsushi Hazeyama, Kozaburo Kurita, Koki Tsutsumida
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Patent number: 9209111Abstract: A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.Type: GrantFiled: July 2, 2014Date of Patent: December 8, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kenichi Watanabe, Tomoji Nakamura, Satoshi Otsuka
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Publication number: 20140312507Abstract: A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.Type: ApplicationFiled: July 2, 2014Publication date: October 23, 2014Inventors: Kenichi WATANABE, Tomoji NAKAMURA, Satoshi OTSUKA
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Patent number: 8791570Abstract: A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.Type: GrantFiled: May 29, 2012Date of Patent: July 29, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Tomoji Nakamura, Satoshi Otsuka
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Publication number: 20140070863Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).Type: ApplicationFiled: November 19, 2013Publication date: March 13, 2014Applicant: Hitachi, Ltd.Inventors: Yasuyoshi Sunaga, Hideki Sakakibara, Yuko Ito, Tomoji Nakamura, Atsushi Hazeyama, Kozaburo Kurita, Koki Tsutsumida
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Patent number: 8299619Abstract: A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second cType: GrantFiled: January 28, 2011Date of Patent: October 30, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Tomoji Nakamura, Satoshi Otsuka
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Publication number: 20120261833Abstract: A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.Type: ApplicationFiled: May 29, 2012Publication date: October 18, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kenichi WATANABE, Tomoji NAKAMURA, Satoshi OTSUKA
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Patent number: 8207610Abstract: A structure device having a multilayer interconnection structure; such a structure includes at least a first interconnection layer and a second interconnection layer; the first interconnection layer includes a first conductor pattern embedded in a first interlayer insulation film and a second conductor pattern embedded in said first interlayer insulation film; the second interconnection layer includes a third conductor pattern embedded in a second interlayer insulation film; the third conductor pattern being coupled to an extension part in a part thereof so as to extend in said second interlayer insulation film in a plane of said second interlayer insulation film; the extension part of said third conductor pattern, said first via-plug and said second viaplug forming help form a dual damascene structure.Type: GrantFiled: November 14, 2007Date of Patent: June 26, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Tomoji Nakamura, Satoshi Otsuka
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Patent number: 8037384Abstract: A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.Type: GrantFiled: December 19, 2008Date of Patent: October 11, 2011Assignee: Hitachi, Ltd.Inventors: Takumi Hasegawa, Motoyuki Sato, Tomoji Nakamura, Nobuo Konami, Jun Matsushima
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Publication number: 20110121460Abstract: A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second cType: ApplicationFiled: January 28, 2011Publication date: May 26, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kenichi WATANABE, Tomoji Nakamura, Satoshi Otsuka
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Publication number: 20110074385Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).Type: ApplicationFiled: August 3, 2010Publication date: March 31, 2011Inventors: Yasuyoshi Sunaga, Hideki Sakakibara, Yuko Ito, Tomoji Nakamura, Atsushi Hazeyama, Kozaburo Kurita, Koki Tsutsumida
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Patent number: 7633148Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.Type: GrantFiled: February 15, 2007Date of Patent: December 15, 2009Assignee: Fujitsu LimitedInventors: Yuji Awano, Masataka Mizukoshi, Taisuke Iwai, Tomoji Nakamura
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Publication number: 20090172488Abstract: A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.Type: ApplicationFiled: December 19, 2008Publication date: July 2, 2009Inventors: Takumi Hasegawa, Motoyuki Sato, Tomoji Nakamura, Nobuo Konami, Jun Matsushima
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Publication number: 20080142977Abstract: A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second cType: ApplicationFiled: November 14, 2007Publication date: June 19, 2008Applicant: FUJITSU LIMITEDInventors: Kenichi WATANABE, Tomoji NAKAMURA, Satoshi OTSUKA
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Publication number: 20070267735Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.Type: ApplicationFiled: February 15, 2007Publication date: November 22, 2007Applicant: FUJITSU LIMITEDInventors: Yuji Awano, Masataka Mizukoshi, Taisuke Iwai, Tomoji Nakamura
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Patent number: 7069774Abstract: A crank angle detecting device that is independent of fluctuations in engine rotational speed and reliably detects a reference crank angle position. A ring gear fixed to a crankshaft of a single cylinder engine has plural projections (teeth) formed around its outer periphery at equal intervals and one irregular interval portion (toothless portion). A crank angle sensor detects start and end on both sides of each projection, a lateral length of each projection and an interval of two adjacent projections, and calculates a ratio therebetween to distinguish the irregular interval portion from the projections. The crank angle sensor and the irregular interval portion are so positioned that the irregular interval portion is detected when the piston is close to bottom dead center.Type: GrantFiled: October 8, 2002Date of Patent: July 4, 2006Assignee: Yamaha Hatsudoki Kabushiki KaishaInventors: Tomoji Nakamura, Toshihiko Yamashita
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Patent number: 6978768Abstract: To provide an acceleration control method for an engine, which determines the accelerating state appropriately without a sensor, a mechanism, or the like specially added for determining the accelerating state and performs suitable acceleration control, while it prevents acceleration misdetermination at engine start or at an extremely low engine speed to improve engine startability and drivability at an extremely low engine speed.Type: GrantFiled: October 8, 2002Date of Patent: December 27, 2005Assignee: Yamaha Hatsudoki Kabushiki KaishaInventors: Toshihiko Yamashita, Tomoji Nakamura
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Patent number: 6922803Abstract: A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns.Type: GrantFiled: March 20, 2001Date of Patent: July 26, 2005Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.Inventors: Michinobu Nakao, Kazumi Hatayama, Koichiro Natsume, Yoshikazu Kiyoshige, Masaki Kouno, Masato Hamamoto, Hidefumi Yoshida, Tomoji Nakamura