Abstract: A data processing apparatus has a latch circuit between a processing unit and a memory. Processed data produced by the processing unit is not directly written into a working area of the memory, but is temporarily stored in the latch circuit. A write operation of the processed data stored in the latch circuit is executed in parallel with a read operation for reading the next data to be processed out of the memory and/or an executing operation of the processing unit. Therefore, processing speed is much improved. In addition, the processed data in the latch circuit can be directly transferred to the processing unit without first having to be written into the memory.

Abstract: A full adder has a carry producing circuit responsive to at least two input bits and a low order carry bit and producing a carry bit, and a sum producing circuit responsive to the two input bits, the low order carry bit and the carry bit and producing a sum bit, wherein the sum producing circuit is provided with a first sum producing portion activated in the co-presence of the two input bits of logic "1" level or logic "0" level and the low order carry bit of logic "1" level or logic "0" level to produce the sum bit, and a second sum producing portion activated in the co-presence of at least one of the input bits and the low order carry bit different in logic level from the other bits to produce the sum bit opposite in logic level to the carry bit, so that signal propagation path is reduced in length, thereby achieving a high speed operation.

Abstract: A program skip operation control system used in a prefetched processor includes at least a program memory for storing a number of instructions, an instruction register associated to the program memory to fetch an instruction to be executed, and an instruction decoder receiving the content of the instruction register so as to generate a decoded instruction. An instruction address register is associated to the program memory to updateably prefetch an address of an instruction to be next fetched from the program memory to the instruction register, so that in the course of execution of the decoded instruction outputted from the instruction decoder, an instruction to be next executed is fetched from the program memory to the instruction register. The instruction decoder responds to a skip signal so as to invalidate the decoded instruction and generate a no-operation instruction for at least one cycle after a predetermined skip operation has been carried out.

Abstract: An improved data processing IC chip which can be fabricated with a reduced area is disclosed. The data processing chip includes a plurality of memory blocks provided at different locations. The memory blocks are adapted to be selected by decoded outputs. Each of the memory blocks is provided with a unit decoding circuit for producing a decoded output therefor and the unit decoding circuit is located close to the associated memory block.

Abstract: A shift control circuit comprising an arithmetic circuit for producing a string of a predetermined number of data bits, a logic circuit for detecting the positive or negative sign of the bit string and producing a first switch signal responsive to the positive sign of the bit string or a second switch signal responsive to the negative sign of the bit string, a one's complement generator circuit for producing a signal representative of the one's complement of the bit string, a first selective signal transfer circuit such as a multiplexer which is transparent directly to the bit string in response to the first switch signal or to the signal from the one's complement generator circuit in response to the second switch signal, a decoder circuit for decoding the bit string or the signal passed through the first selective signal transfer circuit for producing a decoded output signal, a single-bit shifter circuit for shifting the bit of the decoded output signal by a single bit in a predetermined direction for produc

Abstract: A floating-point normalizing circuit is adapted to receive two multi-bit numbers so as to generate a signal indicative of a shift amount for floating-point normalization. The normalizing comprises a plurality of unitary circuits each including a pair of binary inputs, a unitary shift signal output, a carry input, a carry output internally but disconnectably connected to the carry input. These unitary circuits are adapted to receive at their binary inputs different digit position bits of each of the two input numbers, respectively, but each of the unitary circuits receives at its one pair of binary inputs the same digit position bits of the two input numbers. The carry input of each unitary circuit is connected to the carry output of an adjacent more significant digit unitary circuit so that a carry signal is transferred from a more significant digit unitary circuit to a less significant digit unitary circuit.

Abstract: A floating-point data rounding and normalizing circuit comprises a shift controller receiving a fraction portion of an input floating-point data for generating a shift control signal indicative of a shift amount required for normalization. A barrel shifter receives the fraction portion of the input floating-point data and is controlled by the shift control signal to shift the fraction portion by the required amount. A round circuit receives the shifted fraction portion for rounding it, and if an overflow occurs in the rounding operation by the rounding circuit, it is detected by a detector. A rounded fraction is inputted to another shifter controlled by the overflow detector so as to shift back the rounded fraction output one bit in response to generation of the overflow.

Abstract: In a multiplying operation, a first partial product corresponding to multiplication of the multiplicand by even multipliers can be produced by a shifting operation, while a second partial product corresponding to multiplication of the multiplicand by odd multipliers is produced by a shifting operation and an adding operation. In the described multiplying circuit, the first partial product is produced according to the result of a decoding operation for generating signals designating the partial product to be used in the multiplying operation. On the other hand the second partial product is independently produced regardless of the decoding result when the multiplicand is received to the multiplying circuit. Thus, a high speed multiplying operation can be achieved.

Abstract: A pipeline processing apparatus has a plurality of pipeline stages, each stage including a pipeline latch and a pipeline processing circuit. A pipeline bus serially connects the several pipeline stages such that input data supplied through an input unit can be serially transported through the several pipeline stages and finally to an output unit. To facilitate testing the pipeline processing apparatus and specifically the individual pipeline stages and the data passing through these individual stages independently of the pipeline processing cycle, there is provided a common bus coupled to the input unit, the output unit and selectively to each of the pipeline stages. A designated pipeline stage is selectively coupled to the common bus and to cause test data to be supplied to the designated pipeline stage and subsequently read out from the designated stage.

Abstract: An interface unit for connecting a transmitting unit to a receiving unit, the transmitting being capable of transmitting data at a speed greater than the processing speed of the receiving unit. The interface includes a serially connected multistage register which receives input data from the transmitting unit at its input stage and reads out data stored in its output stage to the receiving unit. It also includes a control circuit and a counter storing a count corresponding to the quantity of data stored in the register, the counter being incremented by one each time data is added to the register and decremented by one each time data is read from the register output stage. The control circuit is composed of a decoder and write control circuit. The decoder provides a signal to the write control circuit indicative of the count in the counter. When a datum is to be received from the transmitting unit, it signals the interface through a gate circuit, this signal incrementing the memory.