Abstract: With respect to a method of determining a split scheme, the method includes calculating, by one or more processors, data related to data transfer time, for each combination of parallelization axes at respective layers of a hierarchical memory computer, based on data transfer methods, a size of a problem to be calculated, and communication bandwidths between the layers. The data transfer methods are determined by the parallelization axes, and the parallelization axes indicate how to split the problem. The method further includes determining, by the one or more processors, a combination of the parallelization axes based on the data related to the data transfer time calculated for each combination of the parallelization axes.

Abstract: A base isolator according to an embodiment is provided between an object to be base-isolated and a foundation, and has an elastic body expanding and contracting to reduce horizontal vibrations generated in the object. The base isolator includes: an anchored portion anchored to the foundation; a base-isolation unit having the elastic body and provided on the anchored portion; a first anchoring groove provided on a first surface which is a surface of the base-isolation unit facing the anchored portion; a second anchoring groove provided on a second surface which is a surface of the anchored portion facing the base-isolation unit. An anchor simultaneously fits into the first and second anchoring grooves such that a horizontal movement of the base-isolation unit with respect to the foundation is restricted. The anchor removes restriction on the horizontal movement of the base-isolation unit when a predetermined force is applied in a horizontal direction.

Abstract: A communication test circuit for allowing a tolerance test to be carried out in a general testing environment. The communication test circuit includes an adder and a second clock generation block. When an offset is input to the adder, the adder adds the offset to a phase adjustment signal for adjusting the phase of a clock signal for data detection and outputs the result to the second clock generation block. The second clock generation block outputs a second clock signal adjusted in accordance with the phase adjustment signal to which the offset has been added. Accordingly, a clock signal shifted in accordance with the offset from a natural clock signal along the time axis is generated at a test.

Abstract: An electrostatic discharge protection circuit and a semiconductor device that prevent the breakdown of a semiconductor device caused by an electrostatic discharge (ESD) which suddenly changes. When voltage which is far higher than VDD1 is applied to a power supply line as a result of an ESD, a great electric potential difference is produced between VDD1 and VSS. At this time an electric current path for making an electric charge generated by overvoltage flow to a grounding line is formed by a clamp circuit. As a result, an electric current flows into GND of a circuit block. This prevents the production of a great electric potential difference between VDD1 and VSS. In addition, at this time a rapid change in the level of the overvoltage applied to a signal line is suppressed by a protection circuit. This prevents the dielectric breakdown of gate oxide films of transistors included in a circuit block which receives a control signal.

Abstract: A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in FIG. 1, positive-phase input signal) whose waveform is to be equalized is input to the source of an nMOS, and this enables the equalizer circuit to handle an input signal with the center voltage 0 V without the need to add an extra circuit. The waveform of the input signal is shaped by a delay circuit including a resistor and a capacitor, and an output signal (in FIG. 1, positive-phase output signal) is output from a node.

Abstract: A transmission device including: a driver unit which generates an output signal having an amplitude by a resistance division of a power-supply voltage; and an output-amplitude correction unit which generates current according to variation in the power-supply voltage, and corrects the amplitude by using the current.

Abstract: A transmission device including: a driver unit which generates an output signal having an amplitude by a resistance division of a power-supply voltage; and an output-amplitude correction unit which generates current according to variation in the power-supply voltage, and corrects the amplitude by using the current.

Abstract: A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in FIG. 1, positive-phase input signal) whose waveform is to be equalized is input to the source of an NMOS, and this enables the equalizer circuit to handle an input signal with the center voltage 0 V without the need to add an extra circuit. The waveform of the input signal is shaped by a delay circuit including a resistor and a capacitor, and an output signal (in FIG. 1, positive-phase output signal) is output from a node.

Abstract: A communication test circuit for allowing a tolerance test to be carried out in a general testing environment. The communication test circuit includes an adder and a second clock generation block. When an offset is input to the adder, the adder adds the offset to a phase adjustment signal for adjusting the phase of a clock signal for data detection and outputs the result to the second clock generation block. The second clock generation block outputs a second clock signal adjusted in accordance with the phase adjustment signal to which the offset has been added. Accordingly, a clock signal shifted in accordance with the offset from a natural clock signal along the time axis is generated at a test.

Abstract: An electrostatic discharge protection circuit and a semiconductor device that prevent the breakdown of a semiconductor device caused by an electrostatic discharge (ESD) which suddenly changes. When voltage which is far higher than VDD1 is applied to a power supply line as a result of an ESD, a great electric potential difference is produced between VDD1 and VSS. At this time an electric current path for making an electric charge generated by overvoltage flow to a grounding line is formed by a clamp circuit. As a result, an electric current flows into GND of a circuit block. This prevents the production of a great electric potential difference between VDD1 and VSS. In addition, at this time a rapid change in the level of the overvoltage applied to a signal line is suppressed by a protection circuit. This prevents the dielectric breakdown of gate oxide films of transistors included in a circuit block which receives a control signal.

Abstract: An output circuit has a data control circuit, a variable resistance circuit, a common-mode voltage detection circuit, an adjusting circuit. The data control circuit controls data included in an output signal according to an input signal, the variable resistance circuit is connected in series with the data control circuit between a first power supply line and a second power supply line. Further, the common-mode voltage detection circuit detects a common-mode voltage of the output signal, and the adjusting circuit adjusts a resistance of the variable resistance circuit according to an output of the common-mode voltage detection circuit. The common-mode voltage of the output signal is adjusted to equal an optional voltage, and an amplitude of the output signal is adjustable.

Abstract: An output circuit has a data control circuit, a variable resistance circuit, a common-mode voltage detection circuit, an adjusting circuit. The data control circuit controls data included in an output signal according to an input signal, the variable resistance circuit is connected in series with the data control circuit between a first power supply line and a second power supply line. Further, the common-mode voltage detection circuit detects a common-mode voltage of the output signal, and the adjusting circuit adjusts a resistance of the variable resistance circuit according to an output of the common-mode voltage detection circuit. The common-mode voltage of the output signal is adjusted to equal an optional voltage, and an amplitude of the output signal is adjustable.