Patents by Inventor Tomokazu Kaneko
Tomokazu Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230401832Abstract: Provided is an information processing apparatus causing an image identification model to perform learning in consideration between a degree of similarity between an original image and a converted image.Type: ApplicationFiled: June 2, 2023Publication date: December 14, 2023Applicant: NEC CorporationInventors: Ryosuke Sakai, Soma Shiraishi, Tomokazu Kaneko
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Publication number: 20230386180Abstract: In a learning data generation device, an acquisition means acquires a first image corresponding to an image obtained by photographing one or more objects arranged in a predetermined arrangement state, and first information corresponding to information indicating the predetermined arrangement state in the first image. An image deformation means deforms a second image corresponding to an image of a desired object. An image generation means generates a fourth image having an arrangement state that matches or is similar to the predetermined arrangement state indicated by the first image, by pasting a deformed second image to the first image or a third image corresponding to the image of a position where the desired object is arranged. A learning data generation means generates data including the fourth image and second information corresponding to the information indicating the arrangement state of the object in the fourth image, as learning data.Type: ApplicationFiled: May 25, 2023Publication date: November 30, 2023Applicant: NEC CorporationInventors: Tomokazu KANEKO, Soma Shiraishi, Ryosuke Sakai
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Publication number: 20230215152Abstract: In a learning device, a feature extraction means extracts image features from an input image. A class discrimination means discriminate a class of the input image based on the image features, and generates a class discriminative result. A class discriminative loss calculation means calculates a class discriminative loss based on the class discriminative result. A normal/abnormal discrimination means discriminates whether the class is a normal class or an abnormal class, based on the image features, and generates a normal/abnormal discriminative result. The AUC loss calculation means calculates an AUC loss based on the normal/abnormal result. A first learning means updates parameters of the feature extraction means, a class discrimination means, and the normal/abnormal discrimination means, based on the class discriminative loss and the AUC loss.Type: ApplicationFiled: June 3, 2020Publication date: July 6, 2023Applicant: NEC CorporationInventors: Tomokazu Kaneko, Makoto Terao
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Publication number: 20220254136Abstract: An image acquisition unit 110 acquires a plurality of images. The plurality of images include an object to be inferred. An image cut-out unit 120 cuts out an object region including the object from each of the plurality of images acquired by the image acquisition unit 110. An importance generation unit 130 generates importance information by processing the object region cut out by the image cut-out unit 120. The importance information indicates the importance of the object region when an object inference model is generated, and is generated for each object region, that is, for each image acquired by the image acquisition unit 110. A learning data generation unit 140 stores a plurality of object regions cut out by the image cut-out unit 120 and a plurality of pieces of importance information generated by the importance generation unit 130 in a learning data storage unit 150 as at least a part of the learning data.Type: ApplicationFiled: January 28, 2022Publication date: August 11, 2022Applicant: NEC CorporationInventors: Tomokazu KANEKO, Katsuhiko TAKAHASHI, Makoto TERAO, Soma SHIRAISHI, Takami SATO, Yu NABETO, Ryosuke SAKAI
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Publication number: 20160217845Abstract: An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (CKE) controller. The CKE controller controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested. At a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode. At a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.Type: ApplicationFiled: July 28, 2015Publication date: July 28, 2016Applicant: FUJI XEROX CO., LTD.Inventors: Tsutomu NAKAMINATO, Yoshinobu TERUI, Tomokazu KANEKO, Katsuma NAKAMOTO, Yoshitaka TERUI, Asahito SHIOYASU
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Patent number: 9396788Abstract: An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (CKE) controller. The CKE controller controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested. At a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode. At a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.Type: GrantFiled: July 28, 2015Date of Patent: July 19, 2016Assignee: FUJI XEROX CO., LTD.Inventors: Tsutomu Nakaminato, Yoshinobu Terui, Tomokazu Kaneko, Katsuma Nakamoto, Yoshitaka Terui, Asahito Shioyasu
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Patent number: 8060693Abstract: A data processing apparatus includes: a storage that has first to nth storage areas and stores data in the first to nth storage areas; a specific area erasion section that erases the data stored in the first storage area of the storage; a area erasion section that erases the data stored in at least one of the second to nth storage areas; and a erasion control section that controls the specific area erasion section and the area erasion section so that erasion of the specific area erasion section takes precedence over erasion of the area erasion section, wherein n is natural number.Type: GrantFiled: December 28, 2006Date of Patent: November 15, 2011Assignee: Fuji Xerox Co., Ltd.Inventors: Nobukazu Miyoshi, Tomokazu Kaneko
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Publication number: 20070271427Abstract: A data processing apparatus includes: a storage that has first to nth storage areas and stores data in the first to nth storage areas; a specific area erasion section that erases the data stored in the first storage area of the storage; a area erasion section that erases the data stored in at least one of the second to nth storage areas; and a erasion control section that controls the specific area erasion section and the area erasion section so that erasion of the specific area erasion section takes precedence over erasion of the area erasion section, wherein n is natural number.Type: ApplicationFiled: December 28, 2006Publication date: November 22, 2007Applicant: FUJI XEROX CO., LTD.Inventors: Nobukazu Miyoshi, Tomokazu Kaneko
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Patent number: 7176785Abstract: While a general-purpose interface circuit and another general-purpose interface circuit are provided so as to transmit/receive data between a host appliance and a device appliance, when the general-purpose interface of the device appliance happens to hang up, a control section transmits a reset signal via a dedicated interface circuit. When a dedicated interface circuit provided on the side of the device appliance receives this reset signal and then outputs this received reset signal to the general-purpose interface circuit, the general-purpose interface circuit is reinitiated.Type: GrantFiled: October 25, 2002Date of Patent: February 13, 2007Assignee: Fuji Xerox Co., Ltd.Inventors: Kazuya Edogawa, Hiroshi Sugita, Kenichi Sonobe, Hirota Takahashi, Tsutomu Hoshino, Tomokazu Kaneko
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Patent number: 7159132Abstract: A USB device for performing communications with a second device through a USB interface while supplying electric power to the second device through a power-source supplying line in the USB interface. The USB device includes a communication unit for communicating with the second device, a power source capable of outputting electric power of a voltage being different from a standard power voltage prescribed in the standards of the USB interface. The power source supplies the electric power to the second device through the power-source supplying line. The second device includes a low load unit and a high load unit The power source supplies the electric power having a power voltage higher than the standard power voltage to the high load unit through the power-source supplying line.Type: GrantFiled: December 17, 2002Date of Patent: January 2, 2007Assignee: Fuji Xerox Co., Ltd.Inventors: Hirota Takahashi, Hiroshi Sugita, Kenichi Sonobe, Kazuya Edogawa, Tomokazu Kaneko, Tsutomu Hoshino
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Patent number: 7124307Abstract: A USB device for supplying current to a device connected thereto through a USB interface. In this USB device, current values requested by the devices are preset, as detecting current values, in detector registers of current detecting parts. The current detecting parts constantly monitor current values of electric powers supplied to the devices. Each current detecting part compares a related detecting current value with a related supplied current value. If the supplied current value exceeds the detecting current value, the current detecting part informs a current detection control part of abnormality occurrence. The current detection control part sets a bit in a no-good status register, which corresponds to the current detecting part having informed the abnormality occurrence, and interrupts a CPU. In turn, the CPU refers to the no-good status register and specifies the failure device, and interrupts a current supplying path connecting to the failure device.Type: GrantFiled: December 27, 2002Date of Patent: October 17, 2006Assignee: Fuji Xerox Co., Ltd.Inventors: Hiroshi Sugita, Kenichi Sonobe, Tomokazu Kaneko, Hirota Takahashi, Kazuya Edogawa, Tsutomu Hoshino
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Patent number: 7010640Abstract: In a CPU, a FET is turned off and power is not supplied to a power supply element of a transceiver for a period of time until predetermined initialization processing, which is implemented in a peripheral device when power is supplied via a cable from a host PC, has been concluded (i.e., a period of time until it becomes possible for the peripheral device to initiate data communication with the host PC). Thus, even if the peripheral device and the host PC are physically connected by a cable, data signals transmitted along signal lines are not relayed by the transceiver to a logic controller, whereby it in effect becomes possible to set the peripheral device in a pseudo-non-connected state with respect to the host PC.Type: GrantFiled: December 9, 2002Date of Patent: March 7, 2006Assignee: Fuji Xerox Co., Ltd.Inventors: Tsutomu Hoshino, Hiroshi Sugita, Kenichi Sonobe, Hirota Takahashi, Kazuya Edogawa, Tomokazu Kaneko
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Publication number: 20030172312Abstract: A USB device for performing communications with a second device through a USB interface while supplying electric power to the second device through a power-source supplying line in the USB interface. The USB device includes a communication unit for communicating with the second device, a power source capable of outputting electric power of a voltage being different from a standard power voltage prescribed in the standards of the USB interface. The power source supplies the electric power to the second device through the power-source supplying line. The second device includes a low load unit and a high load unit The power source supplies the electric power having a power voltage higher than the standard power voltage to the high load unit through the power-source supplying line.Type: ApplicationFiled: December 17, 2002Publication date: September 11, 2003Applicant: FUJI XEROX CO., LTD.Inventors: Hirota Takahashi, Hiroshi Sugita, Kenichi Sonobe, Kazuya Edogawa, Tomokazu Kaneko, Tsutomu Hoshino
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Publication number: 20030172318Abstract: A USB device for supplying current to a device connected thereto through a USB interface. In this USB device, current values requested by the devices are preset, as detecting current values, in detector registers of current detecting parts. The current detecting parts constantly monitor current values of electric powers supplied to the devices. Each current detecting part compares a related detecting current value with a related supplied current value. If the supplied current value exceeds the detecting current value, the current detecting part informs a current detection control part of abnormality occurrence. The current detection control part sets a bit in a no-good status register, which corresponds to the current detecting part having informed the abnormality occurrence, and interrupts a CPU. In turn, the CPU refers to the no-good status register and specifies the failure device, and interrupts a current supplying path connecting to the failure device.Type: ApplicationFiled: December 27, 2002Publication date: September 11, 2003Applicant: FUJI XEROX CO., LTD.Inventors: Hiroshi Sugita, Kenichi Sonobe, Tomokazu Kaneko, Hirota Takahashi, Kazuya Edogawa, Tsutomu Hoshino
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Publication number: 20030115400Abstract: In a CPU, a FET is turned off and power is not supplied to a power supply element of a transceiver for a period of time until predetermined initialization processing, which is implemented in a peripheral device when power is supplied via a cable from a host PC, has been concluded (i.e., a period of time until it becomes possible for the peripheral device to initiate data communication with the host PC). Thus, even if the peripheral device and the host PC are physically connected by a cable, data signals transmitted along signal lines are not relayed by the transceiver to a logic controller, whereby it in effect becomes possible to set the peripheral device in a pseudo-non-connected state with respect to the host PC.Type: ApplicationFiled: December 9, 2002Publication date: June 19, 2003Applicant: FUJI XEROX CO., LTD.Inventors: Tsutomu Hoshino, Hiroshi Sugita, Kenichi Sonobe, Hirota Takahashi, Kazuya Edogawa, Tomokazu Kaneko
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Publication number: 20030088318Abstract: While a general-purpose interface circuit and another general-purpose interface circuit are provided so as to transmit/receive data between a host appliance and a device appliance, when the general-purpose interface of the device appliance happens to hang up, a control section transmits a reset signal via a dedicated interface circuit. When a dedicated interface circuit provided on the side of the device appliance receives this reset signal and then outputs this received reset signal to the general-purpose interface circuit, the general-purpose interface circuit is reinitiated.Type: ApplicationFiled: October 25, 2002Publication date: May 8, 2003Applicant: Fuji Xerox Co., Ltd.Inventors: Kazuya Edogawa, Hiroshi Sugita, Kenichi Sonobe, Hirota Takahashi, Tsutomu Hoshino, Tomokazu Kaneko