Patents by Inventor Tomokazu Otani

Tomokazu Otani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10092834
    Abstract: Provided is a method that includes generating sets of rendering commands for rendering video content for a client device and directing each of the sets of rendering commands to at least one rendering resource from a group of at least two rendering resources, such that each of the rendering resources has at least some of the sets of rendering commands directed to it. The action of directing may include directing each set of rendering commands to a rendering resource, from among the at least two rendering resources, that is designated as an allocated rendering resource for the client device. The method may further include changing which of the at least two rendering resources is designated as the allocated rendering resource for the client device.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 9, 2018
    Assignee: KABUSHIKI KAISHA SQUARE ENIX HOLDINGS
    Inventors: Stephan Georgiev, Tomokazu Otani, Sanro Zlobec
  • Publication number: 20160059125
    Abstract: Provided is a method that includes generating sets of rendering commands for rendering video content for a client device and directing each of the sets of rendering commands to at least one rendering resource from a group of at least two rendering resources, such that each of the rendering resources has at least some of the sets of rendering commands directed to it. The action of directing may include directing each set of rendering commands to a rendering resource, from among the at least two rendering resources, that is designated as an allocated rendering resource for the client device. The method may further include changing which of the at least two rendering resources is designated as the allocated rendering resource for the client device.
    Type: Application
    Filed: May 23, 2013
    Publication date: March 3, 2016
    Applicant: KABUSHIKI KAISHA SQUARE ENIX HOLDINGS (ALSO TRADING AS SQUARE ENIX HOLDINGS CO., LTD.)
    Inventors: Stephan GEORGIEV, Tomokazu OTANI, Sanro ZLOBEC
  • Publication number: 20040178485
    Abstract: A semiconductor device includes a plurality of semiconductor elements each having a plurality of arranged pads, and the semiconductor elements are stacked and housed in the semiconductor device. The semiconductor device further includes a power supply frame that is bar-shaped and supplies a power voltage to at least two of the plurality of semiconductor elements.
    Type: Application
    Filed: October 17, 2003
    Publication date: September 16, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tomokazu Otani, Jun Nakai
  • Patent number: 6784529
    Abstract: A semiconductor device of the present invention includes the multi-stacked structure having the bottom semiconductor package with BGA or PGA terminals so that the total number of terminals of the semiconductor device can be increased without increasing the mounting area. In particular, the semiconductor device includes a first semiconductor package having an upper and lower surfaces. The first semiconductor package has a plurality of land terminals on the lower surface. The semiconductor device also includes a second semiconductor package having a planar configuration substantially the same as that of the first semiconductor package, which is provided on the upper surface of the first semiconductor package. The second semiconductor package has a plurality of lead terminals extending from a side surface of the second semiconductor package.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: August 31, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuya Fukuda, Tomokazu Otani
  • Publication number: 20030127721
    Abstract: A semiconductor device of the present invention includes the multi-stacked structure having the bottom semiconductor package with BGA or PGA terminals so that the total number of terminals of the semiconductor device can be increased without increasing the mounting area. In particular, the semiconductor device includes a first semiconductor package having an upper and lower surfaces. The first semiconductor package has a plurality of land terminals on the lower surface. The semiconductor device also includes a second semiconductor package having a planer configuration substantially the same as that of the first semiconductor package, which is provided on the upper surface of the first semiconductor package. The second semiconductor package has a plurality of lead terminals extending from a side surface of the second semiconductor package.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 10, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tatsuya Fukuda, Tomokazu Otani