Abstract: In a semiconductor integrated circuit device having a DRAM 30, the DRAM 30 has an internal refresh period measuring circuit 20. Supplied with a test mode command as an external command, a command decode portion 32 delivers a test mode signal TM1 to the internal refresh period measuring circuit 20, supplies external clocks CLK as reference clocks ICLK to the internal refresh period measuring circuit 20, and thereafter activates a self-refresh control circuit 33. When activated, the self-refresh control circuit 33 delivers an internal oscillation signal LOSC or OSC having a self-refresh period to the internal refresh period measuring circuit 20. The internal refresh period measuring circuit 20 counts the number of the reference clocks supplied during a self-refresh period of the internal oscillation signal.

Abstract: in a semiconductor integrated circuit device having a DRAM 30, the DRAM 30 has an internal refresh period measuring circuit 20. Supplied with a test mode command as an external command, a command decode portion 32 delivers a test mode signal TM1 to the internal refresh period measuring circuit 20, supplies external clocks CLK as reference clocks ICLK to the internal refresh period measuring circuit 20, and thereafter activates a self-refresh control circuit 33. When activated, the self-refresh control circuit 33 delivers an internal oscillation signal LOSC or OSC having a self-refresh period to the internal refresh period measuring circuit 20. The internal refresh period measuring circuit 20 counts the number of the reference clocks supplied during a self-refresh period of the internal oscillation signal.