Patents by Inventor Tomoki Higashi
Tomoki Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11923015Abstract: According to one embodiment, a semiconductor storage device includes strings each with a first select transistor, memory cell transistors, and a second select transistor connected in series. Word lines are provided, each connected to memory cell transistors in a same position across the strings. A bit line is connected in common to a first end of each of the strings. A source line is connected in common to a second end of each of the strings. A control circuit is configured to perform an erase operation on strings. The control circuit adjusts, for each of the strings, either an application time of a first voltage applied to a gate of the first select transistor of the respective string in the erase operation or a voltage level of the first voltage applied to the gate of the first select transistor of the respective string in the erase operation.Type: GrantFiled: February 28, 2022Date of Patent: March 5, 2024Assignee: Kioxia CorporationInventors: Shinichi Oosera, Sumito Ohtsuki, Tomoki Higashi, Yuki Soh
-
Publication number: 20230087334Abstract: According to one embodiment, a semiconductor storage device includes strings each with a first select transistor, memory cell transistors, and a second select transistor connected in series. Word lines are provided, each connected to memory cell transistors in a same position across the strings. A bit line is connected in common to a first end of each of the strings. A source line is connected in common to a second end of each of the strings. A control circuit is configured to perform an erase operation on strings. The control circuit adjusts, for each of the strings, either an application time of a first voltage applied to a gate of the first select transistor of the respective string in the erase operation or a voltage level of the first voltage applied to the gate of the first select transistor of the respective string in the erase operation.Type: ApplicationFiled: February 28, 2022Publication date: March 23, 2023Inventors: Shinichi OOSERA, Sumito Ohtsuki, Tomoki Higashi, Yuki Soh
-
Patent number: 10803950Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: GrantFiled: May 23, 2019Date of Patent: October 13, 2020Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
-
Publication number: 20190279716Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: ApplicationFiled: May 23, 2019Publication date: September 12, 2019Applicant: Toshiba Memory CorporationInventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
-
Patent number: 10347338Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: GrantFiled: September 8, 2017Date of Patent: July 9, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
-
Patent number: 10255979Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.Type: GrantFiled: March 9, 2018Date of Patent: April 9, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shimura, Shinichi Oosera, Junichi Kijima, Tomoki Higashi, Sumito Ohtsuki, Tomohiro Oda, Keisuke Yonehama
-
Publication number: 20190088342Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.Type: ApplicationFiled: March 9, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIMURA, Shinichi Oosera, Junichi Kijima, Tomoki Higashi, Sumito Ohtsuki, Tomohiro Oda, Keisuke Yonehama
-
Publication number: 20180268906Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: ApplicationFiled: September 8, 2017Publication date: September 20, 2018Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIMURA, Tomoki HIGASHI, Sumito OHTSUKI, Junichi KIJIMA, Keisuke YONEHAMA, Shinichi OOSERA, Yuki KANAMORI, Hidehiro SHIGA, Koki UENO
-
Publication number: 20160240261Abstract: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.Type: ApplicationFiled: April 25, 2016Publication date: August 18, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hitoshi IWAI, Tomoki HIGASHI, Shinichi OOSERA
-
Publication number: 20140313829Abstract: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.Type: ApplicationFiled: July 1, 2014Publication date: October 23, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hitoshi IWAI, Tomoki HIGASHI, Shinichi OOSERA
-
Patent number: 8804427Abstract: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.Type: GrantFiled: December 2, 2013Date of Patent: August 12, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Iwai, Tomoki Higashi, Shinichi Oosera
-
Patent number: 8750017Abstract: According to one embodiment, a resistance-change memory includes bit lines, word lines, a memory cell array including memory cells arranged at intersections between the bit lines and the word lines, each of the memory cells including a variable-resistance element and a diode, a control circuit configured to apply a reverse bias to the diode, and to write data to a selected memory cell, and a current limiting circuit configured to limit a current flowing to the selected memory cell in a write. The current limiting circuit controls the current flowing to the selected memory cell not to exceed a second compliance current obtained by adding a leakage current from an unselected memory cell to a predetermined first compliance current.Type: GrantFiled: January 26, 2012Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Mizuki Kaneko, Tomoki Higashi, Tomonori Kurosawa
-
Publication number: 20140085991Abstract: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hitoshi IWAI, Tomoki HIGASHI, Shinichi OOSERA
-
Patent number: 8659947Abstract: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.Type: GrantFiled: April 25, 2013Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Iwai, Tomoki Higashi, Shinichi Oosera
-
Publication number: 20130229876Abstract: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.Type: ApplicationFiled: April 25, 2013Publication date: September 5, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hitoshi IWAI, Tomoki Higashi, Shinichi Oosera
-
Patent number: 8493796Abstract: A nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells having a charge storage layer and a control electrode; and a control unit configured to execute a write cycle multiple times, the write cycle including a write operation and a write verify operation, the write operation being an operation for applying a write pulse voltage multiple times to the control electrode selected for data write, and the write verify operation being an operation for determining whether data write is completed or not. During one time of the write operation, the control unit makes a voltage value of a finally applied write pulse voltage larger than a voltage value of an initially applied write pulse voltage.Type: GrantFiled: September 22, 2011Date of Patent: July 23, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tomoki Higashi, Kazumi Tanimoto
-
Publication number: 20120243294Abstract: According to one embodiment, a resistance-change memory includes bit lines, word lines, a memory cell array including memory cells arranged at intersections between the bit lines and the word lines, each of the memory cells including a variable-resistance element and a diode, a control circuit configured to apply a reverse bias to the diode, and to write data to a selected memory cell, and a current limiting circuit configured to limit a current flowing to the selected memory cell in a write. The current limiting circuit controls the current flowing to the selected memory cell not to exceed a second compliance current obtained by adding a leakage current from an unselected memory cell to a predetermined first compliance current.Type: ApplicationFiled: January 26, 2012Publication date: September 27, 2012Inventors: Mizuki Kaneko, Tomoki Higashi, Tomonori Kurosawa
-
Publication number: 20120134212Abstract: A nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells having a charge storage layer and a control electrode; and a control unit configured to execute a write cycle multiple times, the write cycle including a write operation and a write verify operation, the write operation being an operation for applying a write pulse voltage multiple times to the control electrode selected for data write, and the write verify operation being an operation for determining whether data write is completed or not. During one time of the write operation, the control unit makes a voltage value of a finally applied write pulse voltage larger than a voltage value of an initially applied write pulse voltage.Type: ApplicationFiled: September 22, 2011Publication date: May 31, 2012Applicant: Kabushiki Kaisha ToshibaInventors: TOMOKI HIGASHI, KAZUMI TANIMOTO
-
Publication number: 20120069660Abstract: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.Type: ApplicationFiled: March 7, 2011Publication date: March 22, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Hitoshi IWAI, Tomoki HIGASHI, Shinichi OOSERA
-
Publication number: 20110069556Abstract: A NAND flash memory has a memory cell transistor, the memory cell transistor including a charge storage layer formed over a well of a semiconductor substrate surface via a first insulation film and insulated from surroundings, and a control gate provided over the charge storage layer via a second insulation film, the memory cell transistor storing information according to a threshold voltage which depends on a charge quantity retained by the charge storage layer; and a control circuit which controls operation of the memory cell transistor by controlling a voltage applied to the control gate and a voltage applied to the well.Type: ApplicationFiled: August 24, 2010Publication date: March 24, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Tomoki HIGASHI, Kazumi Tanimoto