Patents by Inventor Tomoki Nakagawa

Tomoki Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101748
    Abstract: A polyurethane dispersion is an aqueous dispersion of a polyurethane resin. The polyurethane resin is a reaction product of an isocyanate group-terminated prepolymer and a chain extender. The isocyanate group-terminated prepolymer includes a reaction product of a polyisocyanate component containing a xylylene diisocyanate, and an active hydrogen group-containing component containing a short-chain diol having 2 to 6 carbon atoms and an active hydrogen group-containing compound containing a hydrophilic group. The chain extender includes an ethylenediamine. A ratio of the ethylenediamine is 25 mol % or more with respect to the total amount of the chain extender.
    Type: Application
    Filed: January 18, 2022
    Publication date: March 28, 2024
    Inventors: Toshihiko NAKAGAWA, Kazuyuki FUKUDA, Tomoki SUGIHARA
  • Publication number: 20230307051
    Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.
    Type: Application
    Filed: August 26, 2022
    Publication date: September 28, 2023
    Inventors: Tomoki NAKAGAWA, Koji KATO, Shuhei OKETA, Mai SHIMIZU
  • Patent number: 11763570
    Abstract: An obstacle detection device includes a stereo camera that captures IR images on the right side and left side; a point cloud data creation unit that creates point cloud data having three-dimensional position information from the IR images captured by the stereo camera; an obstacle detection unit that detects an obstacle according to point cloud data; an invalid area identification unit that identifies whether an invalid area with no point cloud is present in point cloud data; and a target recognition unit that recognizes a particular target in the invalid area with no point cloud according to an IR image. When a particular target is recognized by the target recognition unit, the obstacle detection unit does not determine the invalid area with no point cloud to be an obstacle.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: September 19, 2023
    Assignee: Alps Alpine Co., LTD.
    Inventors: Kaoru Mashiko, Tomoki Nakagawa, Tatsuya Matsui
  • Publication number: 20230224779
    Abstract: A radio terminal (1) determines that the radio terminal (1) is approaching a first station (5), receives from a center server (4) a cell identifier of a first cell corresponding to an entrance gate function (53) of the first station (5), and transmit a message containing the cell identifier to a cellular communication network. The message causes the network to add the first cell (54) as a secondary cell in dual connectivity for the radio terminal (1), enabling the radio terminal (1) to communicate with the entrance gate function (53) via a user plane path including a radio connection of the first cell (54). The radio terminal (1) then communicates with the entrance gate function (53) via the user plane path. This contributes, for example, to reducing latency required to transmit or receive user data in a narrow coverage cell when a radio terminal receives a signal from that cell.
    Type: Application
    Filed: April 26, 2021
    Publication date: July 13, 2023
    Applicant: NEC Corporation
    Inventors: Toshiyuki TAMURA, Junya OKABE, Kazuhiro CHIBA, Kouji SHIMIZU, Tomoki NAKAGAWA, Takahiro AOKI
  • Publication number: 20220319590
    Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 6, 2022
    Inventors: Tomoki NAKAGAWA, Koji KATO, Toshifumi HASHIMOTO
  • Publication number: 20220295363
    Abstract: A Policy Control Function (PCF) apparatus (34) receives information from a Network Exposure Function (NEF) apparatus (35) or an Application Function (AF) apparatus (41) and modifies based on the information a policy including an Index to RAT/Frequency Selection Priority (RFSP index). This can, for example, contribute to enabling a radio communication network to provide a User Equipment (UE) with a user plane path containing a radio connection in a specific cell based on a request from an AF.
    Type: Application
    Filed: April 26, 2021
    Publication date: September 15, 2022
    Applicant: NEC Corporation
    Inventors: Toshiyuki TAMURA, Junya OKABE, Kazuhiro CHIBA, Kouji SHIMIZU, Tomoki NAKAGAWA, Takahiro AOKI
  • Publication number: 20220264679
    Abstract: A User Equipment (UE) (3) includes, in a Non-Access Stratum (NAS) message requesting establishment or modification of a protocol data unit (PDU) session, one or both of a first identifier representing a candidate secondary cell (12) for dual connectivity and a second identifier representing a frequency band in which the candidate secondary cell operates. The UE (3) sends the NAS message to a core network (30) via a radio access network (10). This can, for example, allow a radio communication network to provide a UE with a user plane path that includes a radio connection in a specific secondary cell of dual connectivity based on a request from the UE or an application function.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 18, 2022
    Applicant: NEC Corporation
    Inventors: Toshiyuki TAMURA, Junya OKABE, Kazuhiro CHIBA, Kouji SHIMIZU, Tomoki NAKAGAWA, Takahiro AOKI
  • Patent number: 11393525
    Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoki Nakagawa, Koji Kato, Toshifumi Hashimoto
  • Publication number: 20220084586
    Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
    Type: Application
    Filed: February 25, 2021
    Publication date: March 17, 2022
    Inventors: Tomoki NAKAGAWA, Koji KATO, Toshifumi HASHIMOTO
  • Publication number: 20220004783
    Abstract: An obstacle detection device includes a stereo camera that captures IR images on the right side and left side; a point cloud data creation unit that creates point cloud data having three-dimensional position information from the IR images captured by the stereo camera; an obstacle detection unit that detects an obstacle according to point cloud data; an invalid area identification unit that identifies whether an invalid area with no point cloud is present in point cloud data; and a target recognition unit that recognizes a particular target in the invalid area with no point cloud according to an IR image. When a particular target is recognized by the target recognition unit, the obstacle detection unit does not determine the invalid area with no point cloud to be an obstacle.
    Type: Application
    Filed: June 23, 2021
    Publication date: January 6, 2022
    Applicant: ALPS ALPINE CO., LTD.
    Inventors: Kaoru Mashiko, Tomoki Nakagawa, Tatsuya Matsui
  • Patent number: 10262740
    Abstract: A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoki Nakagawa, Koji Hosono
  • Publication number: 20180277220
    Abstract: A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.
    Type: Application
    Filed: February 5, 2018
    Publication date: September 27, 2018
    Inventors: Tomoki NAKAGAWA, Koji HOSONO
  • Patent number: 9830990
    Abstract: Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: November 28, 2017
    Assignee: Rohm Co., Ltd.
    Inventors: Shintaro Izumi, Tomoki Nakagawa, Hiroshi Kawaguchi, Masahiko Yoshimoto
  • Publication number: 20170278558
    Abstract: Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.
    Type: Application
    Filed: June 7, 2017
    Publication date: September 28, 2017
    Inventors: Shintaro IZUMI, Tomoki NAKAGAWA, Hiroshi KAWAGUCHI, Masahiko Yoshimoto
  • Publication number: 20160111138
    Abstract: Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.
    Type: Application
    Filed: May 29, 2015
    Publication date: April 21, 2016
    Inventors: Shintaro IZUMI, Tomoki NAKAGAWA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO
  • Publication number: 20160064037
    Abstract: One embodiment provides a video apparatus including: a recorder configured to record a video content including caption information; a setting register configured to set search parameters including a keyword; and a chapter generator configured to extract chapters each including an interval in which the keyword appears in a caption or captions from the video content. The chapter generator extracts the chapters by setting a start point of a period in which a caption containing the keyword is to be displayed first as a chapter start point, and setting a point that comes first after the end of display of a tail caption containing the keyword among a point when a silent interval starts, a point when a prescribed time elapses, and an end point of a packet concerned of the video content consisting of plural packets as a chapter end point.
    Type: Application
    Filed: February 19, 2015
    Publication date: March 3, 2016
    Inventors: Megumi Miyazaki, Tomoki Nakagawa
  • Publication number: 20150071608
    Abstract: According to one embodiment, an electronic device includes a subtitle data acquisition module configured to acquire subtitle data from a title being reproduced, a seek instruction receiving module configured to receive an instruction to carry out a seek to an image start point which is a temporal position corresponding to the subtitle data acquired by the subtitle data acquisition module, a title type identifying module configured to identify the type of a title being reproduced at the point in time at which the seek instruction receiving module has received the seek instruction, and a display control module configured to control that the seek is carried out to the image start point corresponding to the subtitle data.
    Type: Application
    Filed: April 3, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroaki Ito, Michio Yamashita, Tomoki Nakagawa
  • Publication number: 20150071604
    Abstract: According to one embodiment, an electronic apparatus includes a processor and a display controller. The processor is configured to acquire a first attribute and a first keyword of content, and to extract a scene including the first keyword in a caption from stored contents having the first attribute. The display controller is configured to cause a scene image representing an extracted scene to be displayed on a display.
    Type: Application
    Filed: February 14, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Michio Yamashita, Hiroaki Ito, Tomoki Nakagawa, Masami Tanaka
  • Publication number: 20150074113
    Abstract: A first database file stores scene list data includes caption data of captions and time data indicative of time to display the captions. A second database file stores keywords. The keywords indicate character strings of the caption data of a program currently being viewed. When an order to display the keywords is input, a keyword list generator reads a plurality of keywords from the second database file and generates a keyword list for display. When an optional keyword is selected, the scene list generator generates scene selection items.
    Type: Application
    Filed: March 3, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroaki Ito, Michio Yamashita, Tomoki Nakagawa
  • Publication number: 20150063782
    Abstract: According to an embodiment, an electronic apparatus includes a processor and a display controller. The processor is configured to acquire keywords from program information of a program being displayed on a screen. The display controller is configured to display the keywords arranged to be selectable on the screen and to display, if a first keyword is selected from the keywords, a first scene information regarding a first scene, a caption of the first scene including the first keyword.
    Type: Application
    Filed: February 14, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Michio Yamashita, Hiroaki Ito, Tomoki Nakagawa