Patents by Inventor Tomoki Noda

Tomoki Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8368833
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: February 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Publication number: 20120236226
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Application
    Filed: September 12, 2011
    Publication date: September 20, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki NODA, Toshihide TSUBATA, Masanori TAKEUCHI, Kenji ENDA
  • Patent number: 8193649
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: June 5, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
  • Patent number: 8089571
    Abstract: An active matrix substrate (12) includes a substrate, a TFT (24) formed on the substrate, a storage capacitor element (20) formed on the substrate, an interlayer insulating film covering the storage capacitor element (20), and a pixel electrode (21) formed on the interlayer insulating film. The storage capacitor element (20) includes a storage capacitor line (27), an insulating film formed on the storage capacitor line (27), and two or more storage capacitor electrodes (25a, 25b, 25c) opposed to the storage capacitor line (27) with the insulating film interposed therebetween. The two or more storage capacitor electrodes (25a, 25b, 25c) are electrically connected via associated contact holes (26a, 26b, 26c) formed in the interlayer insulating film to the pixel electrode (21) and electrically continuous with a drain electrode of the TFT (24).
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: January 3, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshifumi Yagi, Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Publication number: 20110267569
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki NODA, Masanori TAKEUCHI, Kenji ENDA
  • Patent number: 8035768
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: October 11, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Patent number: 8022559
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: September 20, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
  • Patent number: 8008789
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 30, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
  • Publication number: 20110122354
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Application
    Filed: February 1, 2011
    Publication date: May 26, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki NODA, Toshihide TSUBATA, Masanori TAKEUCHI, Kenji ENDA
  • Publication number: 20110096284
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Application
    Filed: December 30, 2010
    Publication date: April 28, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki NODA, Masanori TAKEUCHI, Kenji ENDA
  • Patent number: 7903190
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 8, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Publication number: 20100296020
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Application
    Filed: July 30, 2010
    Publication date: November 25, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki NODA, Toshihide TSUBATA, Masanori TAKEUCHI, Kenji ENDA
  • Patent number: 7777825
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: August 17, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Patent number: 7768584
    Abstract: An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 3, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshifumi Yagi, Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Patent number: 7714948
    Abstract: An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: May 11, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshifumi Yagi, Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Publication number: 20090268116
    Abstract: An active matrix substrate (12) includes a substrate, a TFT (24) formed on the substrate, a storage capacitor element (20) formed on the substrate, an interlayer insulating film covering the storage capacitor element (20), and a pixel electrode (21) formed on the interlayer insulating film. The storage capacitor element (20) includes a storage capacitor line (27), an insulating film formed on the storage capacitor line (27), and two or more storage capacitor electrodes (25a, 25b, 25c) opposed to the storage capacitor line (27) with the insulating film interposed therebetween. The two or more storage capacitor electrodes (25a, 25b, 25c) are electrically connected via associated contact holes (26a, 26b, 26c) formed in the interlayer insulating film to the pixel electrode (21) and electrically continuous with a drain electrode of the TFT (24).
    Type: Application
    Filed: July 2, 2009
    Publication date: October 29, 2009
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Toshifumi Yagi, Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Publication number: 20090262274
    Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.
    Type: Application
    Filed: December 13, 2005
    Publication date: October 22, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Publication number: 20090236760
    Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.
    Type: Application
    Filed: September 15, 2006
    Publication date: September 24, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
  • Publication number: 20090225247
    Abstract: An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 10, 2009
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Toshifumi Yagi, Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda
  • Publication number: 20080002076
    Abstract: An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.
    Type: Application
    Filed: December 14, 2005
    Publication date: January 3, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Toshifumi Yagi, Tomoki Noda, Toshihide Tsubata, Masanori Takeuchi, Kenji Enda