Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.

Abstract: An active matrix substrate (12) includes a substrate, a TFT (24) formed on the substrate, a storage capacitor element (20) formed on the substrate, an interlayer insulating film covering the storage capacitor element (20), and a pixel electrode (21) formed on the interlayer insulating film. The storage capacitor element (20) includes a storage capacitor line (27), an insulating film formed on the storage capacitor line (27), and two or more storage capacitor electrodes (25a, 25b, 25c) opposed to the storage capacitor line (27) with the insulating film interposed therebetween. The two or more storage capacitor electrodes (25a, 25b, 25c) are electrically connected via associated contact holes (26a, 26b, 26c) formed in the interlayer insulating film to the pixel electrode (21) and electrically continuous with a drain electrode of the TFT (24).

Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.

Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.

Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.

Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.

Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Abstract: An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.

Abstract: An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.

Abstract: An active matrix substrate (12) includes a substrate, a TFT (24) formed on the substrate, a storage capacitor element (20) formed on the substrate, an interlayer insulating film covering the storage capacitor element (20), and a pixel electrode (21) formed on the interlayer insulating film. The storage capacitor element (20) includes a storage capacitor line (27), an insulating film formed on the storage capacitor line (27), and two or more storage capacitor electrodes (25a, 25b, 25c) opposed to the storage capacitor line (27) with the insulating film interposed therebetween. The two or more storage capacitor electrodes (25a, 25b, 25c) are electrically connected via associated contact holes (26a, 26b, 26c) formed in the interlayer insulating film to the pixel electrode (21) and electrically continuous with a drain electrode of the TFT (24).

Abstract: A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.

Abstract: An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.

Abstract: An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.