Patents by Inventor Tomoki Satoi

Tomoki Satoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit, semiconductor integrated circuit design support device, and semiconductor integrated circuit manufacturing method
    Patent number: 8028255
    Abstract: A semiconductor integrated circuit including a user logic circuit is disclosed in which circuit parts for shifting data are composed of registers other than scan cells except for the circuit part right after a combinational circuit, and the parts configured of the registers other than the scan cells are used as a scan path.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: September 27, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Tomoki Satoi, Naohiko Nishigaki
  • Scan test circuit, semiconductor integrated circuit and scan enable signal time control circuit
    Patent number: 7836370
    Abstract: A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a practical operation speed, and a controller configured to control the clock generator based on the scan enable signals.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: November 16, 2010
    Assignee: Ricoh Company, Ltd.
    Inventors: Tomoki Satoi, Naohiko Nishigaki
  • SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD
    Publication number: 20080222592
    Abstract: A semiconductor integrated circuit including a user logic circuit is disclosed in which circuit parts for shifting data are composed of registers other than scan cells except for the circuit part right after a combinational circuit, and the parts configured of the registers other than the scan cells are used as a scan path.
    Type: Application
    Filed: February 21, 2008
    Publication date: September 11, 2008
    Inventors: Tomoki Satoi, Naohiko Nishigaki
  • SCAN TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND SCAN ENABLE SIGNAL TIME CONTROL CIRCUIT
    Publication number: 20080222470
    Abstract: A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a practical operation speed, and a controller configured to control the clock generator based on the scan enable signals.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 11, 2008
    Inventors: Tomoki Satoi, Naohiko Nishigaki