Abstract: A data transmitting device includes: a judge code generating portion for transmitting a plurality of times a predefined code pattern indicating a head portion of transmission data, as a judge code; a start code generating portion for transmitting at least once a start code having a predefined code pattern different from the judge code, following the judge code; and a valid data generating portion for transmitting valid data, following the start code. After receiving the judge code for a predetermined number of times that is less by at least one than the number of times that the judge code is transmitted, a data receiving device enters a standby state for receiving the start code, and, after receiving the start code, receives the valid data.

Abstract: A downlink communication data DND from a main control circuit section to a combination control circuit section is divided into first and second downlink data, high-speed communication using a downlink clock signal and a transmission start instruction signal is performed, a high-speed load which has been directly driven from the main control circuit section is indirectly driven at high speed from the combination control circuit section by the first downlink data, a low-speed analog input signal ANL which has been indirectly inputted to the combination control circuit section is inputted to a specific input channel of a multi-channel converter through an indirect multiplexer, and channel selection is made by the downlink communication data.

Abstract: A data transmitting device includes: a judge code generating portion for transmitting a plurality of times a predefined code pattern indicating a head portion of transmission data, as a judge code; a start code generating portion for transmitting at least once a start code having a predefined code pattern different from the judge code, following the judge code; and a valid data generating portion for transmitting valid data, following the start code. After receiving the judge code for a predetermined number of times that is less by at least one than the number of times that the judge code is transmitted, a data receiving device enters a standby state for receiving the start code, and, after receiving the start code, receives the valid data.

Abstract: A downlink communication data DND from a main control circuit section to a combination control circuit section is divided into first and second downlink data, high-speed communication using a downlink clock signal and a transmission start instruction signal is performed, a high-speed load which has been directly driven from the main control circuit section is indirectly driven at high speed from the combination control circuit section by the first downlink data, a low-speed analog input signal ANL which has been indirectly inputted to the combination control circuit section is inputted to a specific input channel of a multi-channel converter through an indirect multiplexer, and channel selection is made by the downlink communication data.

Abstract: A switch state detection circuit according to the present invention comprises: a plurality of switch connection portions to each of which a switch is connected, a connection line to which any one of the switch connection portions is connected in a switchable manner, a detection portion that detects a state of the switch connected to the connection line based on a state of the connection line, and a connection control portion that switches successively each of the switch connection portions and connects it to the connection line, wherein the state of each switch is detected.

Abstract: A circuit control device for controlling power consumption of a plurality of circuit units includes a monitoring unit configured to monitor whether a detection temperature of each of the circuit units meets a predetermined overheat condition, and an overheat protection unit configured to execute an overheat protection operation when the overheat condition is met in any one of the circuit units, wherein the overheat protection operation is an operation to reduce power consumption of an overheat unit meeting the overheat condition, among the circuit units, and a neighbor unit disposed near the overheat unit.

Abstract: A switch state detection circuit according to the present invention comprises: a plurality of switch connection portions to each of which a switch is connected, a connection line to which any one of the switch connection portions is connected in a switchable manner, a detection portion that detects a state of the switch connected to the connection line based on a state of the connection line, and a connection control portion that switches successively each of the switch connection portions and connects it to the connection line, wherein the state of each switch is detected.

Abstract: A circuit control device for controlling power consumption of a plurality of circuit units includes a monitoring unit configured to monitor whether a detection temperature of each of the circuit units meets a predetermined overheat condition, and an overheat protection unit configured to execute an overheat protection operation when the overheat condition is met in any one of the circuit units, wherein the overheat protection operation is an operation to reduce power consumption of an overheat unit meeting the overheat condition, among the circuit units, and a neighbor unit disposed near the overheat unit.

Abstract: A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.

Abstract: A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.

Abstract: There provided is an input device comprising a pressure-sensitive type touch panel; a housing for supporting the touch panel so as to contact the touch panel at a position which is away from a detection area on a surface of the touch panel; and a guide frame which is disposed on the surface of the touch panel so as to be attached to a periphery of an opening portion of the housing and is a member independent from the housing. By employing such an input device, even if the housing is strongly pressed, no erroneous inputting will arise and operability will not be impaired.

Abstract: A game apparatus includes a first LCD, a second LCD, and a microphone disposed between the first LCD and the second LCD. A computer of the game apparatus displays a game image including an object image on at least one of the first LCD and the second LCD. When sound is detected through the microphone, the computer changes the object image displayed on the first LCD and/or the second LCD.