Patents by Inventor Tomoko Inoue
Tomoko Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090036406Abstract: In the case of storing and supplying an injection containing a 2-[(2-pyridyl)methylsulfinyl]benzimidazole type compound in a plastic container in addition to a glass container, an injection having been improved in stability and solubility and showing excellent qualities without forming any insoluble foreign matters or insoluble microparticles can be obtained by using cyclodextrin or its derivative together.Type: ApplicationFiled: June 12, 2006Publication date: February 5, 2009Applicant: TAKEDA PHARMACEUTICAL COMPANY LIMITEDInventors: Shinichiro Nakai, Tomoko Inoue
-
Publication number: 20070212831Abstract: The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9. In the process for forming the bit line 6 on the cell contact interlayer film 8 by etching, the etching for creating an upper surface of the cell contact 9 that is not coupled to the bit line 6 being lower than an upper surface of the cell contact 9 that is coupled to the bit line 6. Further, after the formation of the bit line 6, the barrier metal layer 5 formed on the lower surface of the bit line 6 is selectively etched.Type: ApplicationFiled: May 9, 2007Publication date: September 13, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Tomoko Inoue, Ken Inoue
-
Patent number: 7268380Abstract: The present invention provides a method of increasing designing freedom of a position to form a capacitor, and increasing a capacitance value thereof. When forming a first contact, a tungsten plug for increasing a surface area of a lower electrode is formed in a contact interlayer film at a region where the capacitor is to be formed. Since the tungsten plug does not have to be formed right above the capacitor contact, a position to form the capacitor is not limited by a position where the capacitor contact is provided.Type: GrantFiled: September 16, 2004Date of Patent: September 11, 2007Assignee: NEC Electronics CorporationInventor: Tomoko Inoue
-
Publication number: 20070191286Abstract: An injectable composition comprising a combination of 2-[[[3-methyl-4-(2,2,2-trifluoroethoxy)-2-pyridinyl]methyl]sulfinyl]-1H-benzimidazole (lansoprazole), its optically active compound or a salt thereof, and a chelating agent, which is used at pH 9 to 12. The injectable composition is excellent in stability and solubility, and has such a high-quality that particulate insolubles are not formed when the composition is kept and supplied in a glass container and even in a plastic container and also when the composition is kept in these container for a long time.Type: ApplicationFiled: December 13, 2004Publication date: August 16, 2007Applicant: TAKEDA PHARMACEUTICAL COMPANY LIMITEDInventors: Takayuki Doen, Tomoko Inoue
-
Patent number: 7247904Abstract: A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film without the SAC structure is etched off except where bit line is formed. A direct nitride film is formed on the entire top and side surface of the bit line so as to cover the bit line in one processing step. Since the upper and side nitride film thicknesses are substantially the same, the height of the bit line can be reduced, enabling further miniaturization. In addition, since the sidewall nitride film is formed without an etch back process, it can more easily be formed with a constant film thickness.Type: GrantFiled: April 24, 2006Date of Patent: July 24, 2007Assignee: NEC Electronics CorporationInventors: Tomoko Inoue, Ken Inoue
-
Patent number: 7238980Abstract: The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9. In the process for forming the bit line 6 on the cell contact interlayer film 8 by etching, the etching for creating an upper surface of the cell contact 9 that is not coupled to the bit line 6 being lower than an upper surface of the cell contact 9 that is coupled to the bit line 6. Further, after the formation of the bit line 6, the barrier metal layer 5 formed on the lower surface of the bit line 6 is selectively etched.Type: GrantFiled: August 18, 2004Date of Patent: July 3, 2007Assignee: NEC Electronics CorporationInventors: Tomoko Inoue, Ken Inoue
-
Patent number: 7105882Abstract: The present invention provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process, in which a hard mask is formed on the upper surface of the bit line and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film of the conventional semiconductor device which does not have the SAC structure is etched off except the portion where bit line is formed, and then direct nitride film is formed on the entire surface of the top surface and the side surface of the bit line so as to cover the bit line in a same processing step. Since the film thickness of the nitride film disposed on the upper surface of the bit line is designed to be substantially the same as that disposed on the side surface of the nitride film, the height of the bit line itself can be reduced, and thus a further miniaturization becomes possible.Type: GrantFiled: June 28, 2004Date of Patent: September 12, 2006Assignee: NEC Electronics CorporationInventors: Tomoko Inoue, Ken Inoue
-
Publication number: 20060192236Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed in said first insulating layer in electrically contact with said first transistor in said DRAM portion; a first bit line for said DRAM portion formed on said first insulating layer in electrically contact with said first contact plug; a nitride film formed in contact with said first insulating layer to cover said DRAM portion and said Logic portion, wherein said first bit line locating between said first insulating layer and said nitride film.Type: ApplicationFiled: February 6, 2006Publication date: August 31, 2006Inventors: Tomoko Inoue, Ken Inoue
-
Publication number: 20060186448Abstract: A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film without the SAC structure is etched off except where bit line is formed. A direct nitride film is formed on the entire top and side surface of the bit line so as to cover the bit line in one processing step. Since the upper and side nitride film thicknesses are substantially the same, the height of the bit line can be reduced, enabling further miniaturization. In addition, since the sidewall nitride film is formed without an etch back process, it can more easily be formed with a constant film thickness.Type: ApplicationFiled: April 24, 2006Publication date: August 24, 2006Applicant: NEC ELECTRONICS CORPORATIONInventors: Tomoko Inoue, Ken Inoue
-
Patent number: 7091123Abstract: In a method of forming a metal wiring line, a first insulating film is formed directly or indirectly on a semiconductor substrate. A second insulating film is formed on the first insulating film. A wiring line groove is formed to pass through the second insulating film to an inside of the first insulating film. A conductive film is formed to fill the wiring line groove and to cover the second insulating film. The conductive film and the second insulating film are removed by a first CMP polishing process, using the first insulating film as a stopper film, until the first insulating film is exposed.Type: GrantFiled: August 30, 2002Date of Patent: August 15, 2006Assignee: NEC Electronics CorporationInventors: Takashi Tonegawa, Yasuaki Tsuchiya, Tomoko Inoue
-
Patent number: 7067427Abstract: A method of manufacturing a semiconductor device includes the steps of forming a sunken section in an insulating film formed on a substrate and forming a barrier metal film on the insulating film inclusive of the sunken section. The method also includes forming a copper-based film over the entire surface so as to fill up the sunken section and forming a copper-based metal interconnection. The interconnection is formed by polishing this substrate surface by the chemical mechanical polishing method, using a polishing slurry containing a silica polishing material, an oxidizing agent, an amino acid, a triazole-based compound and water. A content ratio of the amino acid to the triazole-based compound (amino acid/triazole-based compound (weight ratio)) is 5 to 8.Type: GrantFiled: July 15, 2003Date of Patent: June 27, 2006Assignee: NEC Electronics CorporationInventors: Yasuaki Tsuchiya, Tomoko Inoue
-
Publication number: 20050056874Abstract: The present invention provides a method of increasing designing freedom of a position to form a capacitor, and increasing a capacitance value thereof. When forming a first contact, a tungsten plug for increasing a surface area of a lower electrode is formed in a contact interlayer film at a region where the capacitor is to be formed. Since the tungsten plug does not have to be formed right above the capacitor contact, a position to form the capacitor is not limited by a position where the capacitor contact is provided.Type: ApplicationFiled: September 16, 2004Publication date: March 17, 2005Applicant: NEC ELECTRONICS CORPORATIONInventor: Tomoko Inoue
-
Publication number: 20050040449Abstract: The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9. In the process for forming the bit line 6 on the cell contact interlayer film 8 by etching, the etching for creating an upper surface of the cell contact 9 that is not coupled to the bit line 6 being lower than an upper surface of the cell contact 9 that is coupled to the bit line 6. Further, after the formation of the bit line 6, the barrier metal layer 5 formed on the lower surface of the bit line 6 is selectively etched.Type: ApplicationFiled: August 18, 2004Publication date: February 24, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Tomoko Inoue, Ken Inoue
-
Publication number: 20050037590Abstract: The present invention provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process, in which a hard mask is formed on the upper surface of the bit line and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film of the conventional semiconductor device which does not have the SAC structure is etched off except the portion where bit line is formed, and then direct nitride film is formed on the entire surface of the top surface and the side surface of the bit line so as to cover the bit line in a same processing step. Since the film thickness of the nitride film disposed on the upper surface of the bit line is designed to be substantially the same as that disposed on the side surface of the nitride film, the height of the bit line itself can be reduced, and thus a further miniaturization becomes possible.Type: ApplicationFiled: June 28, 2004Publication date: February 17, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Tomoko Inoue, Ken Inoue
-
Patent number: 6815053Abstract: A low thermal expansion laminated plate which has excellent heat resistance, water resistance and toughness and whose average linear expansion coefficient within the temperature ranging from 40 to 150° C. is not higher than 20×10−6/° C. can be obtained by laminating and curing fiber-reinforced layers impregnated with a resin composition consisting of a radically polymerizable resin, radically polymerizable monomer and inorganic filler combined with a specific amount of a thermoplastic resin.Type: GrantFiled: January 2, 2003Date of Patent: November 9, 2004Assignees: Japan Composite Co., Ltd., Matsushita Electric Works, Ltd.Inventors: Tomoko Inoue, Hiroya Okumura, Isao Hirata, Shigehiro Okada
-
Publication number: 20040096680Abstract: A low thermal expansion laminated plate which has excellent heat resistance, water resistance and toughness and whose average linear expansion coefficient within the temperature ranging from 40 to 150° C. is not higher than 20×10−6/° C. can be obtained by laminating and curing fiber-reinforced layers impregnated with a resin composition consisting of a radically polymerizable resin, radically polymerizable monomer and inorganic filler combined with a specific amount of a thermoplastic resin.Type: ApplicationFiled: January 2, 2003Publication date: May 20, 2004Inventors: Tomoko Inoue, Hiroya Okumura, Isao Hirata, Shigehiro Okada
-
Publication number: 20040020135Abstract: A slurry for polishing copper-based metal containing a silica polishing material, an oxidizing agent, an amino acid, a triazole-based compound and water, wherein a content ratio of amino acid to triazole-based compound (amino acid/triazole-based compound (weight ratio)) is 5 to 8.Type: ApplicationFiled: July 21, 2003Publication date: February 5, 2004Applicants: NEC ELECTRONICS CORPORATION, TOKYO MAGNETIC PRINTING CO., LTDInventors: Yasuaki Tsuchiya, Tomoko Inoue, Shin Sakurai, Kenichi Aoyagi, Tetsuyuki Itakura
-
Publication number: 20040023483Abstract: The present invention relates to a method of manufacturing a semiconductor device, comprising the steps of: forming a sunken section in an insulating film formed on a substrate; forming a barrier metal film on said insulating film inclusive of said sunken section; forming a copper-based film over the entire surface so as to fill up said sunken section; and forming a copper-based metal interconnection, which comprises the step of polishing this substrate surface by the chemical mechanical polishing method, using a polishing slurry containing a silica polishing material, an oxidizing agent, an amino acid, a triazole-based compound and water, wherein a content ratio of said amino acid to said triazole-based compound (amino acid/triazole-based compound (weight ratio)) is 5 to 8.Type: ApplicationFiled: July 15, 2003Publication date: February 5, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Yasuaki Tsuchiya, Tomoko Inoue
-
Patent number: 6537358Abstract: In order to provide an yellow recording liquid having superior spray stability, superior preservation stability, and superior water resistance of a recorded image, etc, yellow pigment particles which have been rendered hydrophilic (accepted a sulfonic acid group) at least on the surface (hydrophilic particles) are dispersed in a liquid. In the product yellow recording liquid, the hydrophilic particles are uniformly dispersed and the particles do not aggregate each other. Thus, the uniformly dispersed state of hydrophilic particles as a recording material can be maintained for a long period, thus realizing an yellow recording liquid having a superior spray stability and superior preservation stability. Further, the hydrophilic particles are also hydrophobic by the intrinsic property of the yellow pigment. Thus, the yellow recording liquid has desirable fixability with respect to a surface of a recording medium (recording surface), regardless of whether the recording surface is hydrophilic or hydrophobic.Type: GrantFiled: March 9, 2000Date of Patent: March 25, 2003Assignee: Sharp Kabushiki KaishaInventors: Takahiro Horiuchi, Tomoko Inoue, Masanobu Hasebe
-
Publication number: 20030049927Abstract: In a method of forming a metal wiring line, a first insulating film is formed directly or indirectly on a semiconductor substrate. A second insulating film is formed on the first insulating film. A wiring line groove is formed to pass through the second insulating film to an inside of the first insulating film. A conductive film is formed to fill the wiring line groove and to cover the second insulating film. The conductive film and the second insulating film are removed by a first CMP polishing process, using the first insulating film as a stopper film, until the first insulating film is exposed.Type: ApplicationFiled: August 30, 2002Publication date: March 13, 2003Applicant: NEC CorporationInventors: Takashi Tonegawa, Yasuaki Tsuchiya, Tomoko Inoue