Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.

Abstract: A logic state to be stored at a memory cell of a memory device is determined, where the logic state is to be represented by a threshold voltage stored at the memory cell. A verify reference voltage associated with the logic state is determined. The verify reference voltage defines a target voltage level of the threshold voltage associated with the logic state. The verify reference voltage is updated using an amount of compensation for an expected shift in the threshold voltage of the memory cell after heat is applied to the memory device. Before the heat is applied to the memory device, a plurality of sets of multiple programming pulses to the memory cell is applied until a threshold condition is satisfied. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell to the updated verify reference voltage.

Abstract: A logic state to be stored at a memory cell of a memory device is determined, where the logic state is to be represented by a threshold voltage stored at the memory cell. A verify reference voltage associated with the logic state is determined. The verify reference voltage defines a target voltage level of the threshold voltage associated with the logic state. The verify reference voltage is updated using an amount of compensation for an expected shift in the threshold voltage of the memory cell after heat is applied to the memory device. Before the heat is applied to the memory device, a plurality of sets of multiple programming pulses to the memory cell is applied until a threshold condition is satisfied. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell to the updated verify reference voltage.

Abstract: To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device that has a memory having at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other.

Abstract: To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device that has a memory having at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other.

Abstract: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.

Abstract: To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device includes a memory including at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other. An object of the present invention is to improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element.

Abstract: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.

Abstract: A method of transferring a foreign gene into cells, characterized by involving: the step of transferring into the cells with the use of an adenovirus vector, a first nucleic acid, which has a sequence provided with adeno-associated virus-origin ITRs in both sides of the target foreign gene to be transferred, and a second nucleic acid, which has an adeno-associated virus-origin rep gene and a promoter for expressing this gene and carries a stuffer sequence inserted thereinto sandwiched in two recombinase recognition sequences and located between the rep gene and the promoter; and the step of expressing the Rep protein under the action of recombinase in the cells obtained in the above step to thereby integrate the target foreign gene into the chromosomal DNA.

Abstract: A flexible tube for an endoscope is provided with a spirally-wound tube, a braided tube covering the spirally-wound tube, and a sheath provided on the braided tube. The sheath material is fused and coated on the braided tube to form the sheath. When the sheath material is fused and applied on the braided tube, the sheath material passes through interstices of the braided tube, at the positions facing the clearances between windings, to form a plurality of protruded portions which protruded inward with respect to the braided tube.