Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.

Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.

Abstract: A semiconductor memory device includes first and second planes, first and second latch circuits for the first plane of memory cells, wherein data stored in the first latch circuit is transferred to the first plane of memory cells via the second latch circuit, third and fourth latch circuits for the second plane of memory cells, wherein data stored in the third latch circuit is transferred to the second plane of memory cells via the fourth latch circuit, and a control circuit configured to perform a sequence of operations in response to commands, the sequence of operations including a first operation to transfer first data associated with the commands from the first latch circuit to the second latch circuit and, concurrently with the first operation, a second operation to transfer second data associated with the commands into the third latch circuit.