Patents by Inventor Tomoko Nobutoki
Tomoko Nobutoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8022484Abstract: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.Type: GrantFiled: July 31, 2008Date of Patent: September 20, 2011Assignee: Elpida Memory, Inc.Inventors: Tomoko Nobutoki, Ken Ota
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Publication number: 20080290373Abstract: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Applicant: Elpida Memory, Inc.Inventors: Tomoko Nobutoki, Ken Ota
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Patent number: 7436720Abstract: A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another in which neither of the pair of bit lines is twisted. If an address analysis indicates that there is an access through an input/output wiring, input/output data is not inverted. If the address analysis indicates that there is an access through another input/output wiring and that it is an access to a plate, the input/output data is not inverted, while if it is an access to another plate, the input/output data is inverted.Type: GrantFiled: November 29, 2006Date of Patent: October 14, 2008Assignee: Elpida Memory, Inc.Inventors: Tomoko Nobutoki, Kyoichi Nagata
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Patent number: 7423924Abstract: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.Type: GrantFiled: October 31, 2006Date of Patent: September 9, 2008Assignee: Elpida Memory, Inc.Inventors: Tomoko Nobutoki, Ken Ota
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Publication number: 20070253267Abstract: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.Type: ApplicationFiled: October 31, 2006Publication date: November 1, 2007Inventors: Tomoko Nobutoki, Ken Ota
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Publication number: 20070127301Abstract: A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another in which neither of the pair of bit lines is twisted. If an address analysis indicates that there is an access through an input/output wiring, input/output data is not inverted. If the address analysis indicates that there is an access through another input/output wiring and that it is an access to a plate, the input/output data is not inverted, while if it is an access to another plate, the input/output data is inverted.Type: ApplicationFiled: November 29, 2006Publication date: June 7, 2007Inventors: Tomoko Nobutoki, Kyoichi Nagata
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Patent number: 6181631Abstract: It is an object of the invention to provide a semiconductor memory device with a reduced access time by devising a layout of a circuit without elaborate modification. A Y address buffer is situated on the side of an address pad array (the right side), and outputs a signal for controlling Y address decoder situated on the right side and a circuit block communicated therewith. The Y address decoders on the right side control the Y addresses of memory cells in the memory cell arrays C and D in case that data are read therefrom or written thereinto. The circuit block communicated with the Y address buffer outputs a signal to the address decoders on the side of a DQ pad array (the left side) in accordance with the signal inputted from the Y address buffer. The Y address decoders on the left side control the Y addresses of the memory cells in the memory cell arrays A and B in accordance with the signal inputted from the circuit block communicated with the Y address buffer.Type: GrantFiled: April 22, 1999Date of Patent: January 30, 2001Assignee: NEC CorporationInventors: Tomoko Nobutoki, Kouji Mine
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Patent number: 6122207Abstract: A semiconductor memory device includes a plurality of memory cell groups, the data for the plurality of memory cell groups being transmitted through mutually different buses, and a redundancy memory cell group common to the plurality of memory cell groups. The semiconductor memory device further includes a control circuit for transmitting data for one or more memory cells of the redundancy memory cell group in place of data for one or more defective memory cells in any of the plurality of memory cell groups. Each of the plurality of memory cell groups is provided corresponding to every different input/output terminal of the memory device, or the plurality of memory cell groups are provided corresponding to a common input/output terminal of the memory device.Type: GrantFiled: March 16, 1999Date of Patent: September 19, 2000Assignee: NEC CorporationInventors: Yasuji Koshikawa, Tomoko Nobutoki, Kouji Mine
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Patent number: 6094387Abstract: In a roll call tester, a redundancy circuit is provided which, upon predetermined normal cell addressing, activates the normal cell while rendering the redundancy cell nonactive, and, upon predetermined redundancy cell addressing, renders the normal cell nonactive while, when the roll call test signal in the test signal activation circuit is nonactive, activating the redundancy cell. This construction can realize a roll call test while eliminating the need to use a redundancy detection circuit and a signal involved in the detection thereof, and can reduce chip area.Type: GrantFiled: June 3, 1999Date of Patent: July 25, 2000Assignee: NEC CorporationInventors: Kouji Mine, Yasuji Koshikawa, Tomoko Nobutoki