Patents by Inventor Tomoko Ojima

Tomoko Ojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10153174
    Abstract: A method of manufacturing a semiconductor device according to an embodiment includes forming a first interlayer film on a first layer, the first interlayer film containing a first molecule and a second molecule, and the first molecule and the second molecule being chemically bonded with each other. The method of manufacturing a semiconductor device includes phase-separating the first interlayer film. The method of manufacturing a semiconductor device includes forming a second layer on the phase-separated first interlayer film. The first molecule has a first affinity with the first layer and a second affinity with the second layer, the first affinity being larger than the second affinity. The second molecule has a third affinity with the second layer and a fourth affinity with the first layer, the third affinity being larger than the fourth affinity.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: December 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Tomoko Ojima
  • Publication number: 20160079082
    Abstract: A method of manufacturing a semiconductor device according to an embodiment includes forming a first interlayer film on a first layer, the first interlayer film containing a first molecule and a second molecule, and the first molecule and the second molecule being chemically bonded with each other. The method of manufacturing a semiconductor device includes phase-separating the first interlayer film. The method of manufacturing a semiconductor device includes forming a second layer on the phase-separated first interlayer film. The first molecule has a first affinity with the first layer and a second affinity with the second layer, the first affinity being larger than the second affinity. The second molecule has a third affinity with the second layer and a fourth affinity with the first layer, the third affinity being larger than the fourth affinity.
    Type: Application
    Filed: March 9, 2015
    Publication date: March 17, 2016
    Inventor: TOMOKO OJIMA
  • Publication number: 20150253660
    Abstract: According to one embodiment, a pattern forming method includes: forming a film to be processed on a substrate; forming a resist pattern on the film to be processed; irradiating a predetermined portion of the resist pattern with an energy beam; forming a reversing material layer covering the resist pattern including the portion irradiated with the energy beam; forming a reversed pattern by removing the surface of the reversing material layer so as to expose the portion of the resist pattern not irradiated with the energy beam; removing the resist pattern; and performing an etching process on the film to be processed using the reversed pattern.
    Type: Application
    Filed: July 25, 2014
    Publication date: September 10, 2015
    Inventor: Tomoko OJIMA
  • Publication number: 20140354799
    Abstract: According to one embodiment, a pattern inspection method includes acquiring a first image using a first condition by irradiating an electron beam onto a pattern to be inspected, acquiring a second image using a second condition by irradiating the electron beam onto the pattern, the second condition being different from the first condition, and judging the existence/absence of defects of the pattern by comparing the first image and the second image. A pattern inspection apparatus includes an electron source, a converging part, a stage, an image acquisition part, a controller and a judgment part. The controller is configured to perform a control to acquire a first image using a first condition and acquire a second image using a second condition different from the first condition. The judgment part is configured to judge the existence/absence of defects of the pattern by comparing the first and the second image.
    Type: Application
    Filed: August 15, 2013
    Publication date: December 4, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko OJIMA, Masafumi ASANO
  • Patent number: 8871408
    Abstract: According to one embodiment, a mask pattern creation method includes extracting an area, in which a DSA material is directed self-assembled to form a DSA pattern, from a design pattern area based on a design pattern and information on the DSA material. The method also includes creating a guide pattern that causes the DSA pattern to be formed in the area based on the design pattern, the information on the DSA material, the area, and a design constraint when forming the guide pattern. The method further includes creating a mask pattern of the guide pattern using the guide pattern.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Takekawa, Masafumi Asano, Yingkang Zhang, Kazuhiro Takahata, Tomoko Ojima
  • Publication number: 20130224635
    Abstract: According to one embodiment, a mask pattern creation method includes extracting an area, in which a DSA material is directed self-assembled to form a DSA pattern, from a design pattern area based on a design pattern and information on the DSA material. The method also includes creating a guide pattern that causes the DSA pattern to be formed in the area based on the design pattern, the information on the DSA material, the area, and a design constraint when forming the guide pattern. The method further includes creating a mask pattern of the guide pattern using the guide pattern.
    Type: Application
    Filed: September 5, 2012
    Publication date: August 29, 2013
    Inventors: Yoko TAKEKAWA, Masafumi ASANO, Yingkang ZHANG, Kazuhiro TAKAHATA, Tomoko OJIMA
  • Patent number: 8476170
    Abstract: According to one embodiment, a pattern formation method includes, before forming a circuit pattern on a substrate using imprinting, a wall pattern with a predetermined height is formed to surround the periphery of an area serving as imprint shots on the substrate in each imprint shot and to allow the imprint shots to be separated from one another. The circuit pattern is formed in the imprint shots surrounded by the wall pattern through imprinting.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoko Ojima
  • Publication number: 20120318561
    Abstract: According to one embodiment, a pattern formation method includes: providing a first member; providing a second member; forming a third pattern; and removing a convex portion of a second pattern. The first member is provided on a major surface of a substrate and cured in a state of a template having a first pattern being brought into contact to form the second pattern including a convex portion in a first region on the major surface. The second member is provided in a concave portion adjacent to the convex portion of the second pattern. The third pattern is formed in the second member provided on a second region on the major surface. The removing the convex portion includes removing the convex portion of the second pattern to leave the third pattern and a fourth pattern formed by the second member provided in the concave portion on the major surface.
    Type: Application
    Filed: March 19, 2012
    Publication date: December 20, 2012
    Inventors: Kazuhiro TAKAHATA, Masafumi Asano, Yingkang Zhang, Tomoko Ojima
  • Publication number: 20120149211
    Abstract: According to one embodiment, a pattern formation method includes, before forming a circuit pattern on a substrate using imprinting, a wall pattern with a predetermined height is formed to surround the periphery of an area serving as imprint shots on the substrate in each imprint shot and to allow the imprint shots to be separated from one another. The circuit pattern is formed in the imprint shots surrounded by the wall pattern through imprinting.
    Type: Application
    Filed: September 15, 2011
    Publication date: June 14, 2012
    Inventor: Tomoko OJIMA
  • Publication number: 20110224934
    Abstract: According to one embodiment, an evaluating apparatus includes a resist-pattern-data acquiring unit and an evaluating unit. The resist-pattern-data acquiring unit acquires resist pattern data having a plurality of feature values including at least two among a hole diameter measured concerning a pattern for hole formation in the resist pattern, an aspect ratio of the hole diameter, and a difference of hole diameters at a plurality of signal thresholds. The evaluating unit calculates an evaluation value using an evaluation function for evaluating whether a hole pattern formed on a processing target by using the pattern for hole formation is unopened and the resist pattern data and evaluates presence or absence of a risk that the hole pattern is unopened.
    Type: Application
    Filed: September 15, 2010
    Publication date: September 15, 2011
    Inventors: Seiro Miyoshi, Hideaki Abe, Kazuhiro Takahata, Masafumi Asano, Shoji Mimotogi, Tomoko Ojima, Masanari Kajiwara