Patents by Inventor Tomoko Takizawa

Tomoko Takizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090214629
    Abstract: A method for efficiently transferring a gene to a target cell is provided. A method of transferring a gene to a target cell, including adding or administering a positively charged complex (A) composed of the gene and a cationic substance and gas-filled microparticles (B) to a target cell-containing composition or a living body and then exposing the target cell-containing composition or the living body to a low-frequency ultrasound.
    Type: Application
    Filed: May 26, 2005
    Publication date: August 27, 2009
    Applicant: Mebiopharm Co., Ltd
    Inventors: Kazuo Maruyama, Tomoko Takizawa, Kosuke Hagisawa, Toshihiko Nishioka, Hironobu Yanagie
  • Publication number: 20090110643
    Abstract: Gas-filled liposomes that are useful for ultrasonography and ultrasound therapy are provided. A method of producing the gas-filled liposomes, including filling the void space in a sealed container containing a liposome suspension in a volume amounting to 20 to 80% of the inner capacity thereof with a fluoride gas or a nitrogen gas, and subjecting the container to an ultrasonication.
    Type: Application
    Filed: May 23, 2005
    Publication date: April 30, 2009
    Applicant: MEBIOPHARM CO., LTD.
    Inventors: Kazuo Maruyama, Tomoko Takizawa, Kosuke Hagisawa, Toshihiko Nishioka, Hironobu Yanagie
  • Patent number: 6611063
    Abstract: A method for forming a mold-encapsulated semiconductor device includes the steps of mounting a semiconductor chip on a metallic plate having a metallic interconnect pattern thereon, encapsulating the semiconductor chip on the metallic interconnect pattern, removing the bottom of the metallic plate by etching to expose the metallic interconnect pattern, and forming external terminals on the bottom of the metallic interconnect pattern. The method reduces the thickness as well as the planar dimensions of the semiconductor device.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: August 26, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Michihiko Ichinose, Tomoko Takizawa, Hirokazu Honda, Keiichirou Kata
  • Publication number: 20030119296
    Abstract: Concave portions having shapes adapted to the remaining resist are formed in the vicinities of external terminals of metal wiring. The external terminals of the metal wiring project from the side surfaces of the concave portions. By thus constructing the external terminals, no matter which of the X, Y, and Z directions solder balls that are connected to lands displace in, the lands can displace by following the displacement of the solder balls without restriction. Therefore, even when the semiconductor device and a mounting substrate have elongation differently from each other due to a difference in the coefficient of thermal expansion, the elongation can be absorbed.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 26, 2003
    Inventors: Jun Tsukano, Tomoko Takizawa, Takehiko Maeda
  • Patent number: 6504244
    Abstract: A semiconductor device of the present invention is made up of a semiconductor chip and a single wiring tape resembling a film carrier and including a wiring layer that has a preselected pattern. The wiring tape is adhered to at least the top, bottom and one side of a semiconductor chip. The semiconductor device has outer connecting portions arranged on the above surface of the chip. The semiconductor device is comparable in package size with a bare chip. A semiconductor module having a plurality of such semiconductor devices arranged bidimensionally or tridimensionally achieves desirable electric characteristics while obviating the dense arrangement of a number of wirings.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: January 7, 2003
    Assignee: NEC Corporation
    Inventors: Michihiko Ichinose, Tomoko Takizawa
  • Patent number: 6486553
    Abstract: There is provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making. electrical connection with the semiconductor chip and containing copper (Cu) therein, (c) a solder ball making contact with the wiring and containing tin (Sn) therein, and (d) a layer made of copper-tin (Cu—Sn) alloy, sandwiched between the wiring and the solder ball, and having a thickness equal to or greater than about 1.87 micrometers. The copper-tin alloy layer strengthens connection between the wiring and the solder ball, and hence, ensures reduction in occurrence of breakage and/or cracking in the wiring and the solder ball. As a result, it would be possible to avoid the solder ball from being separated from the wiring due to the breakage and cracking. Accordingly, a fabrication yield of the semiconductor device can be enhanced.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: November 26, 2002
    Assignee: NEC Corporation
    Inventors: Tomoko Takizawa, Masanori Takeuchi
  • Publication number: 20020000651
    Abstract: There is provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making electrical connection with the semiconductor chip and containing copper (Cu) therein, (c) a solder ball making contact with the wiring and containing tin (Sn) therein, and (d) a layer made of copper-tin (Cu—Sn) alloy, sandwiched between the wiring and the solder ball, and having a thickness equal to or greater than about 1.87 micrometers. The copper-tin alloy layer strengthens connection between the wiring and the solder ball, and hence, ensures reduction in occurrence of breakage and/or cracking in the wiring and the solder ball. As a result, it would be possible to avoid the solder ball from being separated from the wiring due to the breakage and cracking. Accordingly, a fabrication yield of the semiconductor device can be enhanced.
    Type: Application
    Filed: July 2, 2001
    Publication date: January 3, 2002
    Inventors: Tomoko Takizawa, Masanori Takeuchi
  • Publication number: 20010010396
    Abstract: A semiconductor device of the present invention is made up of a semiconductor chip and a single wiring tape resembling a film carrier and including a wiring layer that has a preselected pattern. The wiring tape is adhered to at least the top, bottom and one side of a semiconductor chip. The semiconductor device has outer connecting portions arranged on the above surfaces of the chip. The semiconductor device is comparable in package size with a bare chip. A semiconductor module having a plurality of such semiconductor devices arranged bidimensionally or tridimensionally achieves desirable electric characteristics while obviating the dense arrangement of a number of wirings.
    Type: Application
    Filed: January 31, 2001
    Publication date: August 2, 2001
    Inventors: Michihiko Ichinose, Tomoko Takizawa