Patents by Inventor Tomoko Yasunaga

Tomoko Yasunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6218270
    Abstract: A method of manufacturing a semiconductor device having a silicon substrate containing an impurity diffusion layer is disclosed, that comprises the steps of doping impurities to the silicon substrate through a silicon oxide film with a thickness of 2.5 nm or less at an accelerating voltage of 3 keV or less, the silicon oxide film being formed on the silicon substrate and annealing the silicon substrate with the oxide film left.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: April 17, 2001
    Assignee: NEC Corporation
    Inventor: Tomoko Yasunaga
  • Patent number: 6190976
    Abstract: A fabrication method of a semiconductor device with an IGFET is provided, which makes it possible to decrease the current leakage due to electrical short-circuit between a gate electrode and source/drain regions of the IGFET through conductive grains deposited on its dielectric sidewalls. After the basic structure of the IGFET is formed, first and second single-crystal Si epitaxial layers are respectively formed on the first and second source/drain regions by a selective epitaxial growth process. Then, the surface areas of the first and second single-crystal Si epitaxial layers are oxidized, and the oxidized surface areas of the first and second single-crystal Si epitaxial layers are removed by etching.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: February 20, 2001
    Assignee: NEC Corporation
    Inventors: Seiichi Shishiguchi, Tomoko Yasunaga
  • Patent number: 6017823
    Abstract: The present invention provides a method of forming gate side wall insulation films on side walls of a gate electrode on a gate insulation film over a silicon substrate surface. The method comprises The following steps. Gate side wall insulation films are selectively formed on side walls of a gate electrode. A silicon film is selectively grown on at least any one of a top of the gate electrode and on the silicon substrate surface. Surface regions of the gate side wall insulation films are etched.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: January 25, 2000
    Assignee: NEC Corporation
    Inventors: Seiichi Shishiguchi, Tomoko Yasunaga, Akira Mineji