Abstract: A pseudo-random number generation device calculates a value st[i] of b[i] bits by using a function F[i] taking a value st[i?1] as input for each integer value i with i=1, . . . , n in ascending order. The pseudo-random number generation device calculates a value x[i] of r[i] bits by using a function g[i] taking as input at least a part of bits of a value st[j] and at least a part of bits of the value st[i] for at least a part of an integer value i with i=1, . . . , n, where a value j is an integer value smaller than the integer value i. The pseudo-random number generation device combines the values x[i] calculated by using the function g[i] to obtain a pseudo random number.

Abstract: A bit generation apparatus includes a glitch generation circuit that generates glitch signals which include a plurality of pulses, and T-FF bit generation circuits which input the glitch signals, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits generates a respective bit value based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits, circuits that are conventionally required but not essential for the glitch become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit.

Abstract: A bit generation apparatus includes a glitch generation circuit that generates glitch signals which include a plurality of pulses, and T-FF bit generation circuits which input the glitch signals, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits generates a respective bit value based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits, circuits that are conventionally required but not essential for the glitch become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit.

Abstract: An electronic device 100 executes a key-using process that uses a key. A physical quantity generation part 190 generates a physical quantity intrinsic to the electronic device and having a value which is different from one electronic device to another and different each time the physical quantity is generated. A key generation part 140 generates the same key for each key-using process, based on the physical quantity generated by the physical quantity generation part 190, each time the key-using process is to be executed, immediately before the key-using process is started. A key-using process execution part 1010 executes the key-using process such as generation of a keyed hash value, by using the key generated by the key generation part 140. A control program execution part 180 deletes the key generated by the key generation part 140, each time the key-using process is ended.

Abstract: An electronic device 100 executes a key-using process that uses a key. A physical quantity generation part 190 generates a physical quantity intrinsic to the electronic device and having a value which is different from one electronic device to another and different each time the physical quantity is generated. A key generation part 140 generates the same key for each key-using process, based on the physical quantity generated by the physical quantity generation part 190, each time the key-using process is to be executed, immediately before the key-using process is started. A key-using process execution part 1010 executes the key-using process such as generation of a keyed hash value, by using the key generated by the key generation part 140. A control program execution part 180 deletes the key generated by the key generation part 140, each time the key-using process is ended.

Abstract: A sub converter 330 provided in a data conversion apparatus for data encryption/decryption includes a data conversion function and a data transfer function or key transfer function, the sub converter converts data and transfers data that is nonlinear converted in a main converter 320 or a key that is outputted from a key KL register 240, by switching between the data conversion function and the data or key transfer function.

Abstract: A random number sequence is previously generated by the function f8 for data confidentiality processing, which generates a random number sequence, and stored in a random number sequence memory (buffer). When data (message) is input, the random number sequence stored in the random number sequence memory is obtained, and the data (message) is encrypted by an XOR circuit to generate ciphertext data. In case of decrypting data, a random number sequence is also previously generated by the function f8 for data confidentiality processing and stored in the random number sequence memory (buffer). When the ciphertext data is input, by the XOR circuit, the random number sequence stored in the random number sequence memory is read and the ciphertext data is decrypted into the data (message).

Abstract: A sub converter 330 provided in a data conversion apparatus for data encryption/decryption includes a data conversion function and a data transfer function or key transfer function, the sub converter converts data and transfers data that is nonlinear converted in a main converter 320 or a key that is outputted from a key KL register 240, by switching between the data conversion function and the data or key transfer function.

Abstract: A random number sequence is previously generated by the function f8 for data confidentiality processing, which generates a random number sequence, and stored in a random number sequence memory (buffer). When data (message) is input, the random number sequence stored in the random number sequence memory is obtained, and the data (message) is encrypted by an XOR circuit to generate ciphertext data. In case of decrypting data, a random number sequence is also previously generated by the function f8 for data confidentiality processing and stored in the random number sequence memory (buffer). When the ciphertext data is input, by the XOR circuit, the random number sequence stored in the random number sequence memory is read and the ciphertext data is decrypted into the data (message).