Abstract: A diffusion time when forming an isolation region is shortened without deteriorating strength against wafer cracks. A plurality of circular holes 4a and 4b are respectively provided side by side on both surfaces of the wafer discontinuously and intermittently along a scribe line SL between semiconductor devices which are adjacent to each other, and isolation diffusion layers 5a and 5b in a single conductivity type (here, P-type) used for element isolation are respectively formed around the plurality of circular holes 4a and 4b so as to reach a center portion in a depth direction from the both surfaces of the wafer and to be at least partially overlapped with each other between adjacent holes and between upper and lower bottom surfaces.