Abstract: The present invention addresses the problem of providing: an oil and fat composition which is for frozen dessert, moderately lingers, and has a rich flavor with low saturated fatty acid content; and chocolates which are for frozen dessert, and contain the fat and oil composition for frozen dessert. The chocolates which are for frozen dessert, moderately lingers, and has rich flavor with low saturated fatty acid content can be obtained by adding the prescribed amount of a transesterified oil and fat composition which is for frozen dessert and in which the composition of constituent fatty acids and the solid fat content (SFC) have been prescribed.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix and each configured to store data, and a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of the plurality of memory cell transistors, wherein the test circuit includes a plurality of reference cell transistors employed to successively produce varying amounts of currents, a comparison circuit configured to successively compare the amount of test current with each of the varying amounts of currents, and a code generating circuit configured to generate a code indicative of a result of the successive comparisons performed by the comparison circuit, wherein the code is output as the output signal.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix and each configured to store data, and a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of the plurality of memory cell transistors, wherein the test circuit includes a plurality of reference cell transistors employed to successively produce varying amounts of currents, a comparison circuit configured to successively compare the amount of test current with each of the varying amounts of currents, and a code generating circuit configured to generate a code indicative of a result of the successive comparisons performed by the comparison circuit, wherein the code is output as the output signal.