Abstract: In an architecture selection device, an evaluation unit evaluates performance of each of candidates for a combination of processing components to be integrated into a system to be designed. An aggregation unit aggregates costs of each of candidates for a combination of hardware components to be integrated into the system to be designed. A first selection unit and a second selection unit select one combination of the hardware components, as architecture of the system to be designed, from among the candidates for the combination of the hardware components to be integrated into the system to be designed. The combination of the hardware components that is to be selected is a combination of the hardware components which includes a combination of the processing components having the performance evaluated by the evaluation unit satisfying a constraint condition on the performance and whose costs aggregated by the aggregation unit satisfy a constraint condition on the costs.

Abstract: A database stores interface transfer capacity information in which calculation formulas for calculation of a data transfer capacity are described, correspondingly to types of interface circuits. A transfer time evaluation unit acquires a calculation formula corresponding to a type of a specified interface circuit which has been specified from among a plurality of interface circuits as an interface circuit to connect a plurality of arithmetic operational devices among which execution of a plurality of arithmetic operation processes is divided, from the interface transfer capacity information, and calculates the data transfer capacity of the specified interface circuit by using the acquired calculation formula.

Abstract: A processing dividing unit (130) extracts, from a function model (210) including one or more loop processes, each of the one or more loop processes. A parameter extracting unit (140) determines the characteristics of each extracted loop process. A performance calculation basic formula selecting unit (150) selects, for each loop process, from a plurality of processing time calculation procedures for calculating a processing time, a processing time calculation procedure for calculating a processing time of each loop process, based on the characteristics of each loop process and the architecture of computational resources executing the function model (210). A performance estimating unit (160) calculates a processing time of each loop process by using a corresponding processing time calculation procedure selected by the performance calculation basic formula selecting unit (150).

Abstract: An analysis unit divides hierarchized program code into a plurality of program elements in accordance with a predetermined division condition, analyzes each of the plurality of program elements, and extracts an attribute of each program element and a hierarchy of the plurality of program elements. A functional module extraction unit performs machine learning on the basis of the attribute of each program element and the hierarchy of the plurality of program elements extracted by the analysis unit and groups the plurality of program elements into a plurality of groups.