Patents by Inventor Tomomitsu Kitamura
Tomomitsu Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10536154Abstract: In a PLL circuit, a multi-band control oscillator includes multiple bands gradually increasing or decreasing a frequency in accordance with a control signal and being separated from each other, is capable of selectively switching one band among the multiple bands, and generates a signal of a frequency corresponding to the control signal in the band that is switched as a reference signal. A band setting unit sets the band of the multi-band control oscillator. The band setting unit sets the band for a present or subsequent time after a control command generator finishes outputting the control command to gradually increase or decrease from a previous start frequency to a previous stop frequency and before the control command generator starts outputting the control command to gradually increase or decrease from a present start frequency.Type: GrantFiled: July 8, 2019Date of Patent: January 14, 2020Assignee: DENSO CORPORATIONInventor: Tomomitsu Kitamura
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Publication number: 20190334534Abstract: In a PLL circuit, a multi-band control oscillator includes multiple bands gradually increasing or decreasing a frequency in accordance with a control signal and being separated from each other, is capable of selectively switching one band among the multiple bands, and generates a signal of a frequency corresponding to the control signal in the band that is switched as a reference signal. A band setting unit sets the band of the multi-band control oscillator. The band setting unit sets the band for a present or subsequent time after a control command generator finishes outputting the control command to gradually increase or decrease from a previous start frequency to a previous stop frequency and before the control command generator starts outputting the control command to gradually increase or decrease from a present start frequency.Type: ApplicationFiled: July 8, 2019Publication date: October 31, 2019Inventor: Tomomitsu KITAMURA
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Patent number: 9959805Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.Type: GrantFiled: July 25, 2016Date of Patent: May 1, 2018Assignee: Synaptics Japan GKInventors: Keiichi Itoigawa, Yoshihiko Hori, Tomomitsu Kitamura, Takefumi Seno, Hideaki Kuwada, Takashi Tamura, Jun Kurosawa, Kazuhiko Kanda
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Publication number: 20170032757Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.Type: ApplicationFiled: July 25, 2016Publication date: February 2, 2017Inventors: Keiichi ITOIGAWA, Yoshihiko HORI, Tomomitsu KITAMURA, Takefumi SENO, Hideaki KUWADA, Takashi TAMURA, Jun KUROSAWA, Kazuhiko KANDA
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Patent number: 8638142Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: GrantFiled: September 14, 2012Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventors: Ryo Endo, Jiro Shimbo, Tomomitsu Kitamura
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Publication number: 20130009681Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryo ENDO, Jiro SHIMBO, Tomomitsu KITAMURA
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Patent number: 8299828Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: GrantFiled: May 4, 2012Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventors: Ryo Endo, Jiro Shimbo, Tomomitsu Kitamura
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Publication number: 20120212266Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: ApplicationFiled: May 4, 2012Publication date: August 23, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryo ENDO, Jiro SHIMBO, Tomomitsu KITAMURA
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Patent number: 8238839Abstract: Variable operating currents are generated in relation to input signal power and output signal power and achieving both low noise and low power consumption. Emitter follower circuits are attached to output terminals of a frequency divider for generating a local signal. By adjusting the currents flowing through the emitter follower circuits, the amounts of currents flowing into mixers is adjusted. When the amounts of currents of local signals flowing into the mixers increases, the effect of noise suppression is expected. The amounts of the currents flowing through the emitter follower circuits is changed depending on the amplification factor of variable amplifiers.Type: GrantFiled: March 26, 2010Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventors: Norio Hayashi, Satoshi Arayashiki, Takeshi Uchitomi, Tomomitsu Kitamura
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Patent number: 8207767Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: GrantFiled: November 29, 2010Date of Patent: June 26, 2012Assignee: Renesas Electronics CorporationInventors: Ryo Endo, Jiro Shimbo, Tomomitsu Kitamura
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Publication number: 20110140747Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: ApplicationFiled: November 29, 2010Publication date: June 16, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryo ENDO, Jiro SHIMBO, Tomomitsu KITAMURA
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Publication number: 20100297956Abstract: The invention provides a control method for generating variable operating currents in relation to input signal power and output signal power and achieving both low noise and low power consumption. Emitter follower circuits are attached to output terminals of a frequency divider for generating a local signal. By adjusting the currents flowing through the emitter follower circuits, the amount of currents flowing into mixers is adjusted. When the amount of currents of local signals flowing into the mixers increases, the effect of noise suppression is expected. The amount of the currents flowing through the emitter follower circuits is changed depending on the amplification factor of variable amplifiers.Type: ApplicationFiled: March 26, 2010Publication date: November 25, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Norio HAYASHI, Satoshi ARAYASHIKI, Takeshi UCHITOMI, Tomomitsu KITAMURA
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Publication number: 20100052795Abstract: The present invention provides a semiconductor integrated circuit capable of reducing a chip occupied area and reducing variations in control gain of a digitally controlled oscillator. The semiconductor integrated circuit is equipped with the digitally controlled oscillator. The digitally controlled oscillator comprises oscillation transistors and a resonant circuit. The resonant circuit comprises inductances, a frequency coarse-tuning variable capacitor array and a frequency fine-tuning variable capacitor array. The frequency coarse-tuning variable capacitor array comprises a plurality of coarse-tuning capacitor unit cells. The frequency fine-tuning variable capacitor array comprises a plurality of fine-tuning capacitor unit cells. The capacitance values of the coarse-tuning capacitor unit cells of the frequency coarse-tuning variable capacitor array are set in accordance with a binary weight 2M?1.Type: ApplicationFiled: August 12, 2009Publication date: March 4, 2010Inventors: Takahiro Nakamura, Tomomitsu Kitamura, Taizo Yamawaki, Takayasu Norimatsu, Toshiya Uozumi
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Patent number: 7518458Abstract: An LC resonant circuit of an oscillator includes a parallel circuit of an inductor, a first fine adjustable capacitor and a first capacitor bank, and a series circuit of a second fine adjustable capacitor and a second capacitor bank. A frequency conversion gain of the oscillator is the sum of a frequency conversion gain of the oscillator based upon the first fine adjustable capacitor which decreases according to increase of a capacitance value of the capacitor bank and a frequency conversion gain based upon the second fine adjustable capacitor which increases according to increase of a capacitance value of the second capacitor bank. Accordingly, an LC resonant circuit for an oscillator with reduced fluctuation of a frequency conversion gain, and an oscillator and a data processing equipment using the same are provided.Type: GrantFiled: November 8, 2006Date of Patent: April 14, 2009Assignee: Renesas Technology Corp.Inventors: Takahiro Nakamura, Toru Masuda, Tomomitsu Kitamura, Norio Hayashi, Hiroshi Mori
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Patent number: 7336138Abstract: An oscillation circuit formed in a single semiconductor chip, wherein a first source voltage is supplied to a first power supply terminal, a second source voltage different from the first source voltage is supplied to a second power supply terminal, a voltage regulator receives the voltage from the first power supply terminal and outputs a source voltage, a voltage controlled oscillation circuit is supplied with a source voltage from the voltage regulator, a current source circuit is connected to the second power supply terminal, the voltage regulator, the voltage controlled oscillation circuit and the current source circuit are inserted in series between the first and second power supply terminals, and the current supplied to the voltage controlled oscillation circuit from the voltage regulator flows in the current source circuit.Type: GrantFiled: April 28, 2006Date of Patent: February 26, 2008Assignees: Renesas Technology Corp., Epoch Microelectronics, Inc.Inventors: Tomomitsu Kitamura, Ken Suyama, Aleksander Dec
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Publication number: 20070262825Abstract: An oscillation circuit formed in a single semiconductor chip, wherein a first source voltage is supplied to a first power supply terminal, a second source voltage different from the first source voltage is supplied to a second power supply terminal, a voltage regulator receives the voltage from the first power supply terminal and outputs a source voltage, a voltage controlled oscillation circuit is supplied with a source voltage from the voltage regulator, a current source circuit is connected to the second power supply terminal, the voltage regulator, the voltage controlled oscillation circuit and the current source circuit are inserted in series between the first and second power supply terminals, and the current supplied to the voltage controlled oscillation circuit from the voltage regulator flows in the current source circuit.Type: ApplicationFiled: April 28, 2006Publication date: November 15, 2007Inventors: Tomomitsu Kitamura, Ken Suyama, Aleksander Dec
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Publication number: 20070103248Abstract: An LC resonant circuit of an oscillator includes a parallel circuit of an inductor, a first fine adjustable capacitor and a first capacitor bank, and a series circuit of a second fine adjustable capacitor and a second capacitor bank. A frequency conversion gain of the oscillator is the sum of a frequency conversion gain of the oscillator based upon the first fine adjustable capacitor which decreases according to increase of a capacitance value of the capacitor bank and a frequency conversion gain based upon the second fine adjustable capacitor which increases according to increase of a capacitance value of the second capacitor bank. Accordingly, an LC resonant circuit for an oscillator with reduced fluctuation of a frequency conversion gain, and an oscillator and a data processing equipment using the same are provided.Type: ApplicationFiled: November 8, 2006Publication date: May 10, 2007Inventors: Takahiro Nakamura, Toru Masuda, Tomomitsu Kitamura, Norio Hayashi, Hiroshi Mori
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Patent number: 6906596Abstract: A voltage controlled LC resonance oscillation circuit has a plurality of capacitive elements connected to an output node. These capacitive elements are applied with voltages at opposing terminals for selecting an oscillating frequency band, so that the oscillating frequency band can be changed step by step in accordance with the selection voltage. The capacitive elements include at least one variable capacitive element such as a MOS capacitor, the capacitance of which is varied in accordance with a voltage applied thereto. The MOS capacitor is similar in structure to a MOS transistor. The variable capacitive element can be supplied at a terminal opposite to the output node with a voltage from a variable voltage source, for example, in place of the selection voltage. The voltage controlled LC resonance oscillation circuit can measure the output amplitude and oscillating frequency without affecting the characteristics thereof, and reduce the parasitic capacitance.Type: GrantFiled: September 25, 2002Date of Patent: June 14, 2005Assignees: Renesas Technology Corp., Epoch Microelectronics, Inc.Inventors: Tomomitsu Kitamura, Yasuyuki Kimura, Ken Suyama, Aleksander Dec
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Publication number: 20040056725Abstract: A voltage controlled LC resonance oscillation circuit has a plurality of capacitive elements connected to an output node. These capacitive elements are applied with voltages at opposing terminals for selecting an oscillating frequency band, so that the oscillating frequency band can be changed step by step in accordance with the selection voltage. The capacitive elements include at least one variable capacitive element such as a MOS capacitor, the capacitance of which is varied in accordance with a voltage applied thereto. The MOS capacitor is similar in structure to a MOS transistor. The variable capacitive element can be supplied at a terminal opposite to the output node with a voltage from a variable voltage source, for example, in place of the selection voltage. The voltage controlled LC resonance oscillation circuit can measure the output amplitude and oscillating frequency without affecting the characteristics thereof, and reduce the parasitic capacitance.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Inventors: Tomomitsu Kitamura, Yasuyuki Kimura, Ken Suyama, Aleksander Dec