Abstract: The image display device includes an input unit that receives image data, a display unit that displays the image data received by the input unit, a receiving unit that receives drawing data drawn on the image data displayed on the display unit, an output unit that outputs the image data to another device, and a computing unit. The computing unit performs specific image adjustment on the image data, and causes the display unit to display the image data without performing the specific image adjustment on the image data when the specific image adjustment has been performed on the image data received by the input unit.

Abstract: The image display device includes an input unit that receives image data, a display unit that displays the image data received by the input unit, a receiving unit that receives drawing data drawn on the image data displayed on the display unit, an output unit that outputs the image data to another device, and a computing unit. The computing unit performs specific image adjustment on the image data, and causes the display unit to display the image data without performing the specific image adjustment on the image data when the specific image adjustment has been performed on the image data received by the input unit.

Abstract: In the display of an image at a low average picture level, the luminance of black level of the display image is reduced so as to enhance the contrast. In the display of an image at a high average picture level, an address discharge is caused stably. Thereby, the image display quality is enhanced. For this purpose, a specified-cell initializing subfield where a forced initializing waveform is applied to predetermined scan electrodes and a non-initializing waveform is applied to the other scan electrodes in the initializing period, and a selective initializing subfield where a selective initializing waveform is applied to all the scan electrodes in the initializing period are set. A specified-cell initializing field having the specified-cell initializing subfield and the plurality of selective initializing subfields is set.

Abstract: In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.

Abstract: In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.

Abstract: A test of an LSI device under test (20) including a physical layer section (21) which has a high-speed interface function is performed. An LSI device test unit (1) including a reference LSI device (10) which has already been confirmed as being non-defective is placed on a test board (2), and high-speed pins of the LSI devices (10, 20) are connected to each other. An LSI tester (3) accesses logical layer sections (12, 22) at a low speed to control a high-speed communication between physical layer sections (11, 21) and read received data, and determines whether or not the LSI device under test (20) is defective.