Patents by Inventor Tomonaga Itoi

Tomonaga Itoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110016201
    Abstract: A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scale-up type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes. A module management unit responds to system configuration information to switch between a mode in which the node operates singularly as a braid server and a mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and additionally a loop wiring line having a length equal to that of the inter-node link on the back plane is also laid in each node, thereby setting up synchronization among the nodes. Synchronization of reference clocks for SMP coupled nodes is also established.
    Type: Application
    Filed: September 30, 2010
    Publication date: January 20, 2011
    Applicants: HITACHI, LTD., HITACHI INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Toshihiro Ishiki, Naoto Sakuma, Junichi Funatsu, Takeshi Yoshida, Tomonaga Itoi, Morihide Nakaya, Shisei Fujiwara
  • Patent number: 7840675
    Abstract: A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scale-up type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes. A module management unit responds to system configuration information to switch between a mode in which the node operates singularly as a braid server and a mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and additionally a loop wiring line having a length equal to that of the inter-node link on the back plane is also laid in each node, thereby setting up synchronization among the nodes. Synchronization of reference clocks for SMP coupled nodes can be is also established.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 23, 2010
    Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.
    Inventors: Toshihiro Ishiki, Naoto Sakuma, Junichi Funatsu, Takeshi Yoshida, Tomonaga Itoi
  • Publication number: 20060230220
    Abstract: Provided is a fibre channel switch system to which a server and a storage system are connected. The fibre channel switch system includes: a host controller for controlling a fibre channel protocol, to which the server is connected; a management table for indicating a hardware address of the host controller; a switching unit for routing information of the fibre channel protocol; and a control unit for controlling the host controller and the switching unit. Accordingly, the server connected to fibre channel switch system can be downsized.
    Type: Application
    Filed: April 5, 2006
    Publication date: October 12, 2006
    Inventors: Yoshiko Yasuda, Masaji Kume, Tomonaga Itoi
  • Publication number: 20060129585
    Abstract: A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scaleup type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes and a module management unit of each node responds to system configuration information to switch between mode in which the node operates singularly as a braid server and mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and besides a loop wiring line having length equal to that of the inter-node link on back plane is also laid in each node, thereby setting up synchronization among nodes. Each node has a reference clock distribution unit mounted on back plane and adapted to distribute reference clocks to individual nodes and by switching reference clocks by a clock distributor inside each node, synchronization of reference clocks for SMP coupled nodes can be established.
    Type: Application
    Filed: September 16, 2005
    Publication date: June 15, 2006
    Inventors: Toshihiro Ishiki, Naoto Sakuma, Junichi Funatsu, Takeshi Yoshida, Tomonaga Itoi, Morihide Nakaya, Shisei Fujiwara
  • Patent number: 6735686
    Abstract: According to the present invention, instruction decoding can be separated into two stages. In a first instruction decoding stage, multiple instructions are decoded in a single machine cycle. Also, in the first instruction decoding stage, when a branch instruction is decoded a memory is requested to read a branch destination instruction for the branch instruction. The instructions decoded in the first instruction decoding stage is stored temporarily in instruction flow registers. In a second instruction decoding stage, instructions read sequentially from the instruction flow registers are decoded.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: May 11, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tohru Hiraoka, Tomonaga Itoi, Masashi Hakamada