Abstract: A universal logic module of a programmable semiconductor device is constructed by first, second, third, fourth and fifth terminals, a first transfer gate connected between the first and fourth terminals, a second transfer gate connected between the second and fourth terminals, and an inverter connected between the third and fifth terminals. The first and second transfer gates are controlled by voltages at the third and fifth terminals, so that one of the first and second transfer gates is turned ON and the other of the first and second transfer gates is turned OFF.

Abstract: A phase comparator is disclosed that can provide a phase comparison result at high speed that essentially does not vary according a power source voltage, ambient temperature and/or manufacturing process conditions, or the like. A phase comparator (10) may include one-shot pulse generating units (14 and 24) that output one-shot pulses according to input data signal DAT and clock signal CLK, respectively. An R-S flip-flop (16) can receive one-shot pulses from one-shot pulse generating units (14 and 24) at set and reset inputs, respectively. An output flip-flop (17) can select between an output signal of R-S flip-flop (16) and a delay signal “a8” generated from input data signal DAT, and latch such a result according to a delayed clocks signal CLK.

Abstract: A universal logic module of a programmable semiconductor device is constructed by first, second, third, fourth and fifth terminals, a first transfer gate connected between the first and fourth terminals, a second transfer gate connected between the second and fourth terminals, and an inverter connected between the third and fifth terminals. The first and second transfer gates are controlled by voltages at the third and fifth terminals, so that one of the first and second transfer gates is turned ON and the other of the first and second transfer gates is turned OFF.

Abstract: A phase comparator is disclosed that can provide a phase comparison result at high speed that essentially does not vary according a power source voltage, ambient temperature and/or manufacturing process conditions, or the like. A phase comparator (10) may include one-shot pulse generating units (14 and 24) that output one-shot pulses according to input data signal DAT and clock signal CLK, respectively. An R-S flip-flop (16) can receive one-shot pulses from one-shot pulse generating units (14 and 24) at set and reset inputs, respectively. An output flip-flop (17) can select between an output signal of R-S flip-flop (16) and a delay signal “a8” generated from input data signal DAT, and latch such a result according to a delayed clocks signal CLK.

Abstract: A memory cell array included in a content addressable memory stores words, as data to be retrieved, respectively at a plurality of addresses, each of which has been assigned a priority in a descending order. When the data is input, each of a plurality of match detection circuits detects whether the data match the words. A plurality circuit retains, of the retrieval data which have been detected whether the retrieval data matches the corresponding words by the match detection circuits, data stored at an address which is assigned the highest priority, and outputs the data to a retrieval range designation circuit when the following retrieval beings. The retrieval range designation circuit controls each of mask circuits contained in each of the match detection circuits to be in an active state, thereby designating a retrieval range of words within the memory cell array.