Abstract: In a first vertical field-effect transistor in which first source regions and first connectors each of which electrically connects a first body region and a first source electrode are alternately and periodically disposed in a first direction (Y direction) in which a first trench extends, a ratio of LS [?m] to LB [?m] is at least 1/7 and at most 1/3, where LS denotes a length of one of the first source regions in the first direction, and LB denotes a length of one of the first connectors in the first direction, and LB??0.024×(VGS)2+0.633×VGS?0.721 is satisfied for a voltage VGS [V] of a specification value of a semiconductor device, the voltage VGS being applied to a first gate conductor with reference to an electric potential of the first source electrode.

Abstract: In a first vertical field-effect transistor in which first source regions and first connectors each of which electrically connects a first body region and a first source electrode are alternately and periodically disposed in a first direction (Y direction) in which a first trench extends, a ratio of LS [?m] to LB [?m] is at least 1/7 and at most 1/3, where LS denotes a length of one of the first source regions in the first direction, and LB denotes a length of one of the first connectors in the first direction, and LB??0.024×(VGS)2+0.633×VGS?0.721 is satisfied for a voltage VGS [V] of a specification value of a semiconductor device, the voltage VGS being applied to a first gate conductor with reference to an electric potential of the first source electrode.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A shape of an upper edge of a trench is realized as an upwardly-open tapered surface T2, thereby reducing contact resistance without involvement of an increase in pitch for trench formation. Specifically, the trench has the tapered surface along the edge of an opening. A contact surface between a source region and a source electrode filled on the tapered surface makes up a source-contact region.

Abstract: A semiconductor device having trench gates in element regions R1 formed in a semiconductor substrate. Second trenches T2 having the same depth as that of first trenches T1 making up the trench gates are provided along a marginal area of the semiconductor substrate.

Abstract: A shape of an upper edge of a trench is realized as an upwardly-open tapered surface T2, thereby reducing contact resistance without involvement of an increase in pitch for trench formation. Specifically, the trench has the tapered surface along the edge of an opening. A contact surface between a source region and a source electrode filled on the tapered surface makes up a source-contact region.

Abstract: A downwardly convex bowed shape is given to an upper edge Tw2 of each of trenches, whereby contact resistance is reduced without involvement of an increase in pitch at which trenches are to be formed. Specifically, each of the trenches includes a bowed surface Tw2 whose opening edge is outwardly convex when viewed in cross section and a source contact region that is formed between a source electrode filled along the bowed surface Tw2 and a source region formed along the bowed surface Tw2.

Abstract: The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N? layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N? layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N? layer in an area contained in the body layer in plane view.

Abstract: A semiconductor device in the present invention is provided with a cathode layer of an N-type impurity region and an anode layer of a P-type impurity region formed on the cathode layer. A plurality of floating ring layers of the P-type impurity regions which is electrically floating is provided spaced apart from the anode layer on the main surface of the cathode layer. Then, well layers of the N-type impurity regions containing floating ring layers are provided. For example, each well layer can individually be provided to the floating ring layer. In this case, each floating ring layer may be spaced apart or overlapped one another. Accordingly, a semiconductor device serves to downsize a chip without changing a property of on-resistance or a breakdown voltage.

Abstract: The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N? layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N? layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N? layer in an area contained in the body layer in plane view.

Abstract: A semiconductor device includes the following: a well layer formed in the surface region of a silicon layer; a source layer formed in the surface region of the well layer; a high-concentration well layer formed in the well layer so that its depth from the surface of the silicon layer is shallower than the well layer and deeper than the source layer; a gate electrode formed linearly across the silicon layer, the well layer, and the source layer; a first contact region connected electrically to the source layer; second contact regions arranged at predetermined intervals in the direction parallel to the gate electrode within the first contact region and connected electrically to the high-concentration well layer; and a source electrode connected electrically to the first and second contact regions. The source electrode is connected to either the first contact region or the second contact region in any cross section perpendicular to the longitudinal direction of the gate electrode.