Patents by Inventor Tomonari Shioda
Tomonari Shioda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8969891Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.Type: GrantFiled: April 28, 2014Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Taisuke Sato, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20150050763Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.Type: ApplicationFiled: September 25, 2014Publication date: February 19, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu SUGIYAMA, Tomonari SHIODA, Shigeya KIMURA, Koichi TACHIBANA, Shinya NUNOUE
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Patent number: 8952401Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a low refractive index layer. The first semiconductor layer has a first major surface and a second major surface being opposite to the first major surface. The light emitting layer has an active layer provided on the second major surface. The second semiconductor layer is provided on the light emitting layer. The low refractive index layer covers partially the first major surface and has a refractive index lower than the refractive index of the first semiconductor layer.Type: GrantFiled: August 29, 2011Date of Patent: February 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Taisuke Sato, Hiroshi Ono, Satoshi Mitsugi, Tomonari Shioda, Jongil Hwang, Hung Hung, Shinya Nunoue
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Patent number: 8928000Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.Type: GrantFiled: February 27, 2012Date of Patent: January 6, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Tomonari Shioda, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8884307Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.Type: GrantFiled: February 27, 2012Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Tomonari Shioda, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8878213Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.Type: GrantFiled: August 29, 2011Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
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Publication number: 20140319457Abstract: According to one embodiment, a semiconductor light emitting device includes: first and second semiconductor layers, a light emitting part, and an In-containing layer. The first semiconductor layer is formed on a silicon substrate via a foundation layer. The light emitting part is provided on the first semiconductor layer, and includes barrier layers and a well layer provided between the barrier layers including Ga1-z1Inz1N (0<z1?1). The second semiconductor layer is provided on the light emitting part. The In-containing layer is provided at at least one of first and second positions. The first position is between the first semiconductor layer and the light emitting part. The second position is between the second semiconductor layer and the light emitting part. The In-containing layer includes In with a composition ratio different from the In composition ratio z1 and has a thickness 10 nm to 1000 nm.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jongil HWANG, Tomonari SHIODA, Hung HUNG, Naoharu SUGIYAMA, Shinya NUNOUE
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Patent number: 8872158Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part. The n-type semiconductor layer includes a nitride semiconductor. The p-type semiconductor layer includes a nitride semiconductor. The light emitting part is provided between the n-type and the p-type semiconductor layers and includes an n-side barrier layer and a first light emitting layer. The first light emitting layer includes a first barrier layer, a first well layer, and a first AIGaN layer. The first barrier layer is provided between the n-side barrier layer and the p-type semiconductor layer. The first well layer contacts the n-side barrier layer between the n-side and the first barrier layer. The first AIGaN layer is provided between the first well layer and the first barrier layer. A peak wavelength ?p of light emitted from the light emitting part is longer than 515 nanometers.Type: GrantFiled: February 20, 2014Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8835983Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.Type: GrantFiled: October 24, 2013Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Tomonari Shioda, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20140231824Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: TOMONARI SHIODA, HUNG HUNG, JONGIL HWANG, TAISUKE SATO, NAOHARU SUGIYAMA, SHINYA NUNOUE
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Patent number: 8809101Abstract: According to one embodiment, a semiconductor light emitting device includes: first and second semiconductor layers, a light emitting part, and an In-containing layer. The first semiconductor layer is formed on a silicon substrate via a foundation layer. The light emitting part is provided on the first semiconductor layer, and includes barrier layers and a well layer provided between the barrier layers including Ga1?z1Inz1N (0<z1?1). The second semiconductor layer is provided on the light emitting part. The In-containing layer is provided at at least one of first and second positions. The first position is between the first semiconductor layer and the light emitting part. The second position is between the second semiconductor layer and the light emitting part. The In-containing layer includes In with a composition ratio different from the In composition ratio z1 and has a thickness 10 nm to 1000 nm.Type: GrantFiled: August 26, 2011Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jongil Hwang, Tomonari Shioda, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8809085Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor device. The method can include removing a growth substrate from a structure body by using a first treatment material. The structure body has the growth substrate, a buffer layer formed on the growth substrate, and the nitride semiconductor layer formed on the buffer layer. A support substrate is bonded to the nitride semiconductor layer. The method can include reducing thicknesses of the buffer layer and the nitride semiconductor layer by using a second treatment material different from the first treatment material after removing the growth substrate.Type: GrantFiled: August 31, 2011Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Naoharu Sugiyama, Tomonari Shioda, Toshiki Hikosaka, Shinya Nunoue
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Publication number: 20140209013Abstract: A crystal growth method for nitride semiconductors, including the steps of growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate, with the use of a first carrier gas formed with an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer, with the use of a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer, with the use of a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: ApplicationFiled: April 3, 2014Publication date: July 31, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomonari SHIODA, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Patent number: 8790999Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness.Type: GrantFiled: February 25, 2013Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Shinya Nunoue
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Patent number: 8785943Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer, a first stacked intermediate layer, and a functional layer. The foundation layer includes an AlN buffer layer formed on a substrate. The first stacked intermediate layer is provided on the foundation layer. The first stacked intermediate layer includes a first AlN intermediate layer provided on the foundation layer, a first AlGaN intermediate layer provided on the first AlN intermediate layer, and a first GaN intermediate layer provided on the first AlGaN intermediate layer. The functional layer is provided on the first stacked intermediate layer. The first AlGaN intermediate layer includes a first step layer in contact with the first AlN intermediate layer. An Al composition ratio in the first step layer decreases stepwise in a stacking direction from the first AlN intermediate layer toward the first step layer.Type: GrantFiled: February 28, 2012Date of Patent: July 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8779437Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.Type: GrantFiled: August 22, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8759851Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.Type: GrantFiled: July 29, 2013Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Taisuke Sato, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20140166978Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part. The n-type semiconductor layer includes a nitride semiconductor. The p-type semiconductor layer includes a nitride semiconductor. The light emitting part is provided between the n-type and the p-type semiconductor layers and includes an n-side barrier layer and a first light emitting layer. The first light emitting layer includes a first barrier layer, a first well layer, and a first AIGaN layer. The first barrier layer is provided between the n-side barrier layer and the p-type semiconductor layer. The first well layer contacts the n-side barrier layer between the n-side and the first barrier layer. The first AIGaN layer is provided between the first well layer and the first barrier layer. A peak wavelength ?p of light emitted from the light emitting part is longer than 515 nanometers.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Tomonari SHIODA, Hisashi YOSHIDA, Naoharu SUGIYAMA, Shinya NUNOUE
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Patent number: 8728237Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: GrantFiled: September 2, 2010Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Patent number: 8698123Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part. The n-type semiconductor layer includes a nitride semiconductor. The p-type semiconductor layer includes a nitride semiconductor. The light emitting part is provided between the n-type and the p-type semiconductor layers and includes an n-side barrier layer and a first light emitting layer. The first light emitting layer includes a first barrier layer, a first well layer, and a first AlGaN layer. The first barrier layer is provided between the n-side barrier layer and the p-type semiconductor layer. The first well layer contacts the n-side barrier layer between the n-side and the first barrier layer. The first AlGaN layer is provided between the first well layer and the first barrier layer. A peak wavelength ?p of light emitted from the light emitting part is longer than 515 nanometers.Type: GrantFiled: August 19, 2011Date of Patent: April 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue