Patents by Inventor Tomonari Yamamoto
Tomonari Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10748782Abstract: There is provided a method of manufacturing a semiconductor device by processing a substrate, which includes: embedding a polymer having a urea bond in a recess formed in the substrate by supplying a material for polymerization from above a sacrificial film to the substrate and forming a polymer film made of the polymer having the urea bond, wherein a surface of the substrate is covered with the sacrificial film, the recess including an opening of the sacrificial film that is formed by a patterning; removing the polymer film formed on the sacrificial film while leaving the polymer embedded in the recess; removing the sacrificial film in a state in which the polymer is embedded in the recess; and subsequently, removing the polymer embedded in the recess.Type: GrantFiled: October 19, 2018Date of Patent: August 18, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Tatsuya Yamaguchi, Reiji Niino, Makoto Fujikawa, Yoshihiro Hirota, Rong Yang, Tomonari Yamamoto
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Patent number: 10359060Abstract: A moving device includes an elastic tube, a sectional shape of which is elastically deformable according to an internal pressure given by fluid, a slider unit capable of moving forward and backward in a longitudinal direction of the elastic tube according to a change in the sectional shape of the elastic tube, a brake provided in the slider unit and configured to be deformed in a direction perpendicular to the longitudinal direction of the elastic tube to be capable of coming into sliding contact with a target object, and a fluid adjusting section configured to supply air to or discharge air from the elastic tube respectively via first and second fluid supply pipes that respectively communicate with insides on a distal end side and a proximal end side of the elastic tube.Type: GrantFiled: August 25, 2017Date of Patent: July 23, 2019Assignees: Olympus Corporation, NIPO International Rescue System Institute, Tohoku UniversityInventors: Eiichi Kobayashi, Yasuo Hirata, Satoshi Tadokoro, Tomonari Yamamoto, Masashi Konyo, Kenjiro Tadakuma
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Publication number: 20190122894Abstract: There is provided a method of manufacturing a semiconductor device by processing a substrate, which includes: embedding a polymer having a urea bond in a recess formed in the substrate by supplying a material for polymerization from above a sacrificial film to the substrate and forming a polymer film made of the polymer having the urea bond, wherein a surface of the substrate is covered with the sacrificial film, the recess including an opening of the sacrificial film that is formed by a patterning; removing the polymer film formed on the sacrificial film while leaving the polymer embedded in the recess; removing the sacrificial film in a state in which the polymer is embedded in the recess; and subsequently, removing the polymer embedded in the recess.Type: ApplicationFiled: October 19, 2018Publication date: April 25, 2019Inventors: Tatsuya YAMAGUCHI, Reiji NIINO, Makoto FUJIKAWA, Yoshihiro HIROTA, Rong YANG, Tomonari YAMAMOTO
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Publication number: 20170350424Abstract: A moving device includes an elastic tube, a sectional shape of which is elastically deformable according to an internal pressure given by fluid, a slider unit capable of moving forward and backward in a longitudinal direction of the elastic tube according to a change in the sectional shape of the elastic tube, a brake provided in the slider unit and configured to be deformed in a direction perpendicular to the longitudinal direction of the elastic tube to be capable of coming into sliding contact with a target object, and a fluid adjusting section configured to supply air to or discharge air from the elastic tube respectively via first and second fluid supply pipes that respectively communicate with insides on a distal end side and a proximal end side of the elastic tube.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Applicants: OLYMPUS CORPORATION, NPO INTERNATIONAL RESCUE SYSTEM INSTITUTE, TOHOKU UNIVERSITYInventors: Eiichi KOBAYASHI, Yasuo HIRATA, Satoshi TADOKORO, Tomonari YAMAMOTO, Masashi KONYO, Kenjiro TADAKUMA
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Patent number: 9831321Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.Type: GrantFiled: June 13, 2016Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
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Publication number: 20160293735Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.Type: ApplicationFiled: June 13, 2016Publication date: October 6, 2016Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
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Patent number: 9368626Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.Type: GrantFiled: December 4, 2013Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
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Publication number: 20150155383Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.Type: ApplicationFiled: December 4, 2013Publication date: June 4, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
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Patent number: 8912610Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.Type: GrantFiled: April 3, 2012Date of Patent: December 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jr Jung Lin, Yun-Ju Sun, Shih-Hsun Chang, Chia-Jen Chen, Tomonari Yamamoto, Chih-Wei Kuo, Meng-Yi Sun, Kuo-Chiang Ting
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Publication number: 20130119487Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.Type: ApplicationFiled: April 3, 2012Publication date: May 16, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jr Jung Lin, Yun-Ju Sun, Shih-Hsun Chang, Chia-Jen Chen, Tomonari Yamamoto, Chih-Wei Kuo, Meng-Yi Sun, Kuo-Chiang Ting
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Patent number: 8084338Abstract: The depletion of a gate electrode (103) is suppressed in such a way that impurities are introduced into the gate electrode that is formed on a semiconductor substrate (101), with a gate insulating film (102) interposed between the gate electrode (103) and the semiconductor substrate (101), and that, by irradiating a laser beam onto the gate electrode (103), the introduced impurities are made to diffuse up to the interface between the gate electrode (103) and the gate insulating film (102).Type: GrantFiled: June 20, 2005Date of Patent: December 27, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomonari Yamamoto, Kenichi Okabe
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Patent number: 7883960Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.Type: GrantFiled: March 24, 2009Date of Patent: February 8, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Masatoshi Fukuda, Akiyoshi Hatada, Katsuaki Ookoshi, Kenichi Okabe, Tomonari Yamamoto
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Patent number: 7645665Abstract: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.Type: GrantFiled: December 4, 2006Date of Patent: January 12, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Tomohiro Kubo, Kenichi Okabe, Tomonari Yamamoto
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Publication number: 20090311838Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.Type: ApplicationFiled: March 24, 2009Publication date: December 17, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masatoshi FUKUDA, Akiyoshi HATADA, Katsuaki OOKOSHI, Kenichi OKABE, Tomonari YAMAMOTO
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Patent number: 7598162Abstract: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate electrode as a mask (step S7), introducing a diffusion-controlling substance into the semiconductor substrate to control the diffusion of the impurity (step S8), forming a side wall-insulating film on each side surface of the gate electrode (step S9), deeply introducing impurity into the semiconductor substrate using the gate electrode and the side wall-insulating film as masks (step S10), activating the impurity by the annealing treatment using a rapid thermal annealing method (step S11), and further activating the impurity by the millisecond annealing treatment (step S12).Type: GrantFiled: September 26, 2006Date of Patent: October 6, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tomonari Yamamoto, Tomohiro Kubo
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Patent number: 7528031Abstract: After formation of a gate insulating film for a high voltage transistor on the entire surface, when removing the gate insulating film existing within a low voltage region, etching is not finished upon expose of an active region, but over etching is performed until the surface of an element isolation insulating film becomes lower by, for example, about 15 nm than the surface of the active region within the low voltage region. Then, a high-temperature rapid thermal hydrogen treatment is performed on the active region within the low voltage region. As a result of this, a natural oxide film is removed from the surface of the active region within the low voltage region, so that the flatness is increased and its corners are rounded.Type: GrantFiled: September 6, 2006Date of Patent: May 5, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Tomonari Yamamoto
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Patent number: 7432146Abstract: To make it possible to obtain a sharp impurity profile without presenting a disadvantage such as an increase in parasitic resistance or the like using a laser annealing method to thereby meet sufficiently the requirements for making a semiconductor element finer and more highly integrated. A gate electrode is pattern formed above a semiconductor substrate made of n-type silicon single crystal through a gate insulating film. Thereafter, atoms, Ge+ here, having properties just enough to amorphize single crystal Si are ion implanted (shown by arrows) from oblique directions to the Si surface of the substrate with the gate electrode as a mask to melt and re-crystallize the single crystal Si so as to form amorphous regions which seep into the substrate under the gate electrode. Thereafter B+ ions are implanted into the amorphous regions and laser irradiation is executed thereon.Type: GrantFiled: February 27, 2002Date of Patent: October 7, 2008Assignee: Fujitsu LimitedInventor: Tomonari Yamamoto
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Publication number: 20070232039Abstract: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.Type: ApplicationFiled: December 4, 2006Publication date: October 4, 2007Applicant: FUJITSU LIMITEDInventors: Tomohiro Kubo, Kenichi Okabe, Tomonari Yamamoto
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Publication number: 20070072382Abstract: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate electrode as a mask (step S7), introducing a diffusion-suppressing substance into the semiconductor substrate to suppress the diffusion of the impurity (step S8), forming a side wall-insulating film on each side surface of the gate electrode (step S9), deeply introducing impurity into the semiconductor substrate using the gate electrode and the side wall-insulating film as masks (step S10), activating the impurity by the annealing treatment using a rapid thermal annealing method (step S11), and further activating the impurity by the millisecond annealing treatment (step S12).Type: ApplicationFiled: December 14, 2005Publication date: March 29, 2007Applicant: FUJITSU LIMITEDInventors: Tomonari Yamamoto, Tomohiro Kubo
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Publication number: 20070072355Abstract: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate electrode as a mask (step S7), introducing a diffusion-controlling substance into the semiconductor substrate to control the diffusion of the impurity (step S8), forming a side wall-insulating film on each side surface of the gate electrode (step S9), deeply introducing impurity into the semiconductor substrate using the gate electrode and the side wall-insulating film as masks (step S10), activating the impurity by the annealing treatment using a rapid thermal annealing method (step S11), and further activating the impurity by the millisecond annealing treatment (step S12).Type: ApplicationFiled: September 26, 2006Publication date: March 29, 2007Applicant: FUJITSU LIMITEDInventors: Tomonari Yamamoto, Tomohiro Kubo