Abstract: A semiconductor substrate inspection method includes: generating a charged particle beam, and irradiating the charged particle beam to a semiconductor substrate in which contact wiring lines are formed on a surface thereof, the contact wiring lines of the semiconductor substrate being designed to alternately repeat in a plane view so that one of the adjacent contact wiring lines is grounded to the semiconductor substrate and the other of the adjacent contact wiring lines is insulated from the semiconductor substrate; detecting at least one of a secondary charged particle, a reflected charged particle and a back scattering charged particle generated from the surface of the semiconductor substrate to acquire a signal; generating an inspection image with the signal, the inspection image showing a state of the surface of the semiconductor substrate; and judging whether the semiconductor substrate is good or bad from a difference of brightness in the inspection image obtained from the surfaces of the adjacent cont

Abstract: A semiconductor substrate inspection method includes: generating a charged particle beam, and irradiating the charged particle beam to a semiconductor substrate in which contact wiring lines are formed on a surface thereof, the contact wiring lines of the semiconductor substrate being designed to alternately repeat in a plane view so that one of the adjacent contact wiring lines is grounded to the semiconductor substrate and the other of the adjacent contact wiring lines is insulated from the semiconductor substrate; detecting at least one of a secondary charged particle, a reflected charged particle and a back scattering charged particle generated from the surface of the semiconductor substrate to acquire a signal; generating an inspection image with the signal, the inspection image showing a state of the surface of the semiconductor substrate; and judging whether the semiconductor substrate is good or bad from a difference of brightness in the inspection image obtained from the surfaces of the adjacent cont

Abstract: A semiconductor substrate inspection method includes: generating a charged particle beam, and irradiating the charged particle beam to a semiconductor substrate in which contact wiring lines are formed on a surface thereof, the contact wiring lines of the semiconductor substrate being designed to alternately repeat in a plane view so that one of the adjacent contact wiring lines is grounded to the semiconductor substrate and the other of the adjacent contact wiring lines is insulated from the semiconductor substrate; detecting at least one of a secondary charged particle, a reflected charged particle and a back scattering charged particle generated from the surface of the semiconductor substrate to acquire a signal; generating an inspection image with the signal, the inspection image showing a state of the surface of the semiconductor substrate; and judging whether the semiconductor substrate is good or bad from a difference of brightness in the inspection image obtained from the surfaces of the adjacent cont

Abstract: A semiconductor substrate inspection method includes: generating a charged particle beam, and irradiating the charged particle beam to a semiconductor substrate in which contact wiring lines are formed on a surface thereof, the contact wiring lines of the semiconductor substrate being designed to alternately repeat in a plane view so that one of the adjacent contact wiring lines is grounded to the semiconductor substrate and the other of the adjacent contact wiring lines is insulated from the semiconductor substrate; detecting at least one of a secondary charged particle, a reflected charged particle and a back scattering charged particle generated from the surface of the semiconductor substrate to acquire a signal; generating an inspection image with the signal, the inspection image showing a state of the surface of the semiconductor substrate; and judging whether the semiconductor substrate is good or bad from a difference of brightness in the inspection image obtained from the surfaces of the adjacent cont

Abstract: A control system for a manufacturing apparatus includes manufacturing information input unit acquiring time series data of apparatus parameters controlling manufacturing apparatuses; failure pattern classification module classifying in-plane distributions of failures of each of the wafers into failure patterns; an index calculation unit configured to statistically process the time series data by algorithms to calculate indices corresponding to the respective algorithms; an index analysis unit providing first and second frequency distributions of the indices categorized with and without the target failure pattern, to implement significance test between the first and second frequency distributions; and an abnormal parameter extraction unit extracting failure cause index of failure pattern by comparing value of the significance test with test reference value.

Abstract: A control system for a manufacturing apparatus includes manufacturing information input unit acquiring time series data of apparatus parameters controlling manufacturing apparatuses; failure pattern classification module classifying in-plane distributions of failures of each of the wafers into failure patterns; an index calculation unit configured to statistically process the time series data by algorithms to calculate indices corresponding to the respective algorithms; an index analysis unit providing first and second frequency distributions of the indices categorized with and without the target failure pattern, to implement significance test between the first and second frequency distributions; and an abnormal parameter extraction unit extracting failure cause index of failure pattern by comparing value of the significance test with test reference value.

Abstract: An aspect of the present invention provides a system for evaluating mask patterns, including a pattern image generator configured to generate a pattern image of mask patterns to be formed on a mask, a defect generator configured to receive defect data for particles and imaginarily generate defects on the mask according to the defect data, a pattern-defect image generator configured to generate a pattern-defect image of the mask by combining the generated pattern image with the generated defects, a pattern tester configured to determine whether or not each of the defects in the pattern-defect image is allowable according to pattern rules, and a ratio computation unit configured to compute at least one of an allowable ratio and an un allowable ratio according to a determination result from the pattern tester.

Abstract: First wiring pattern data corresponding to a shape of a wiring pattern on a layer in a semiconductor device is acquired on the basis of a first image obtained by imaging a sample which permits imaging of the wiring pattern. Evaluation CAD data which synthesizes CAD data of a plurality of layers, which includes wiring CAD data of the layer with the wiring pattern is generated. Position coordinates of the first wiring pattern data are made to coincide with position coordinates of a wiring pattern contained in the wiring CAD data, and synthesis data is produced by synthesizing the first wiring pattern data and the evaluation CAD data. Based on the synthesis data, a degree of overlapping between the first wiring pattern data and a pattern in the CAD data of a layer other than the layer with the wiring pattern is quantized.

Abstract: Critical location information is used for providing a critical location evaluation method for a semiconductor apparatus pattern. The critical location information includes coordinate information about the critical location and characteristic information indicating a thinning direction and a magnitude thereof at the critical location. Use of this evaluation method can accurately evaluate specification and analysis of thinning or a pattern which makes it difficult to pinpoint a critical location through the visual inspection.

Abstract: A provisional inspection recipe is prepared using a simulated defective wafer having a simulated defect layer which has the variations in height and plane shape with respect to a simulated normal layer. An actual defect inspection for the simulated defective wafer is carried out by means of a defect inspection system to compare a detected defect data with a previously obtained simulated defect data of the simulated defective wafer to quantify a defect detection sensitivity. The provisional inspection recipe is modified while changing tentative recipe parameters until a desired defect detection ratio is obtained. When the desired defect detection ratio is obtained, the tentative recipe parameters at the time are decided as recipe parameters adaptive for the defect inspection system.

Abstract: An aspect of the present invention provides a system for evaluating mask patterns, including a pattern image generator configured to generate a pattern image of mask patterns to be formed on a mask, a defect generator configured to receive defect data for particles and imaginarily generate defects on the mask according to the defect data, a pattern-defect image generator configured to generate a pattern-defect image of the mask by combining the generated pattern image with the generated defects, a pattern tester configured to determine whether or not each of the defects in the pattern-defect image is allowable according to pattern rules, and a ratio computation unit configured to compute at least one of an allowable ratio and an un allowable ratio according to a determination result from the pattern tester.

Abstract: First wiring pattern data corresponding to a shape of a wiring pattern on a layer in a semiconductor device is acquired on the basis of a first image obtained by imaging a sample which permits imaging of the wiring pattern. Evaluation CAD data which synthesizes CAD data of a plurality of layers, which includes wiring CAD data of the layer with the wiring pattern is generated. Position coordinates of the first wiring pattern data are made to coincide with position coordinates of a wiring pattern contained in the wiring CAD data, and synthesis data is produced by synthesizing the first wiring pattern data and the evaluation CAD data. Based on the synthesis data, a degree of overlapping between the first wiring pattern data and a pattern in the CAD data of a layer other than the layer with the wiring pattern is quantized.

Abstract: Critical location information is used for providing a critical location evaluation method for a semiconductor apparatus pattern. The critical location information includes coordinate information about the critical location and characteristic information indicating a thinning direction and a magnitude thereof at the critical location. Use of this evaluation method can accurately evaluate specification and analysis of thinning or a pattern which makes it difficult to pinpoint a critical location through the visual inspection.

Abstract: A provisional inspection recipe is prepared using a simulated defective wafer having a simulated defect layer which has the variations in height and plane shape with respect to a simulated normal layer. An actual defect inspection for the simulated defective wafer is carried out by means of a defect inspection system to compare a detected defect data with a previously obtained simulated defect data of the simulated defective wafer to quantify a defect detection sensitivity. The provisional inspection recipe is modified while changing tentative recipe parameters until a desired defect detection ratio is obtained. When the desired defect detection ratio is obtained, the tentative recipe parameters at the time are decided as recipe parameters adaptive for the defect inspection system.