Abstract: In a LPF (loop filter) 10A, a reference voltage VR achieved through voltage division at resistors 21 and 22 is supplied to the gate of an NMOS 20 to cause a specific level of electrical current to flow into a PMOS 19 and the NMOS 20. The gate voltages at the PMOS 19 and the NMOS 20 are supplied to the gates of a PMOS 17 and an NMOS 18 constituting a current mirror circuit as bias voltages VP and VN. When a detection signal UP or DN is output from a PFD (phase difference detection circuit) 1, the PMOS 17 or the NMOS 18 functions as a high resistance component achieving a high degree of accuracy. The output from a lag lead filter constituted of the on resistances of the PMOS 17 and the NMOS 18, a resistor 15 and a capacitor 16 is provided to a VCO (voltage controlled oscillator circuit) 2 as a control voltage VC, which in turn generates an oscillation signal FV having specific response characteristics.

Abstract: With a VCO 1 which constitutes the voltage controlled oscillator according to the present invention, since NMOS transistors N11, N12 and N13 are provided in each of inverter circuits 11, 12 and 13, the oscillating frequency band can be divided into three sub ranges. As a result, even when the VCO gain effected by a control signal VCN is reduced, a wide frequency band is assured, thereby making it possible to easily support the clock frequency required by the system into which the VCO 1 is to be incorporated.