Patents by Inventor Tomonori Aoyama

Tomonori Aoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250153549
    Abstract: A vehicle side structure includes a door, a protruding member, an engagement portion, and a connection member. The door is configured to open and close a side surface opening of a vehicle body of a vehicle. The protruding member is provided on the door and protrudes outward from an outer plate member of the door. The engagement portion is provided in the vehicle body and is engaged with the protruding member is configured to move inward in a vehicle width direction at a time of side collision of the vehicle. The connection member connects the outer plate member of the door with another member and extends in the vehicle width direction. The connection member has a bend starting point portion serving as a starting point of bending of the connection member at the time of side collision of the vehicle.
    Type: Application
    Filed: October 29, 2024
    Publication date: May 15, 2025
    Applicant: SUBARU CORPORATION
    Inventors: Chihiro YAMAMOTO, Tomonori AOYAMA
  • Patent number: 12240299
    Abstract: A vehicle door structure includes a weather strip part including hard member and soft members that are integrally molded, and includes: a base; a first seal portion in close contact with a protrusion in a fitting portion from a vehicle upper side; a second seal portion in close contact with the fitting portion's vehicle upper side surface; a third seal portion in close contact with a vehicle body; and a fixing portion sandwiching and fixing the protrusion between the first seal portion and the fixing portion. The hard member is continuously provided to pass the second seal portion's vehicle upper side from the base's inner end in the vehicle width direction, have a bent portion towards upward from the vehicle upper side, and further pass the first seal portion and an inside of the fixing portion in the vehicle width direction up to the third seal portion's vehicle upper end.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: March 4, 2025
    Assignee: SUBARU CORPORATION
    Inventor: Tomonori Aoyama
  • Publication number: 20240381647
    Abstract: In one embodiment, a semiconductor device includes a stacked film including a plurality of electrode layers and a plurality of insulating layers alternately stacked in a first direction. The device further includes a columnar portion including a charge storage layer and a first semiconductor layer extending through the stacked film in the first direction, the first semiconductor layer including an impurity element. The device further includes a second semiconductor layer or a first insulator provided on the stacked film and the columnar portion, the second semiconductor layer or the first insulator including the impurity element and having a concentration gradient of the impurity element in the first direction.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Tatsunori ISOGAI, Shunsuke OKADA, Tomonori AOYAMA, Masaki NOGUCHI
  • Publication number: 20240190226
    Abstract: A vehicle door structure includes a weather strip part including hard member and soft members that are integrally molded, and includes: a base; a first seal portion in close contact with a protrusion in a fitting portion from a vehicle upper side; a second seal portion in close contact with the fitting portion's vehicle upper side surface; a third seal portion in close contact with a vehicle body; and a fixing portion sandwiching and fixing the protrusion between the first seal portion and the fixing portion. The hard member is continuously provided to pass the second seal portion's vehicle upper side from the base's inner end in the vehicle width direction, have a bent portion towards upward from the vehicle upper side, and further pass the first seal portion and an inside of the fixing portion in the vehicle width direction up to the third seal portion's vehicle upper end.
    Type: Application
    Filed: November 9, 2023
    Publication date: June 13, 2024
    Inventor: Tomonori AOYAMA
  • Patent number: 11862696
    Abstract: A semiconductor storage device relating to one embodiment includes: a stacked body in which electrode films and insulating films are alternately stacked in a first direction; a first and a second charge storage films that are arranged away from each other in the first direction inside the stacked body and each face one of the electrode films; and a tunnel insulating film that extends in the first direction inside the stacked body and is in contact with the first and the second charge storage films. The first and the second charge storage films each include a first film that is in contact with the electrode film and contains a High-k material, and a second film that is provided between the first film and the tunnel insulating film and contains silicon nitride.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Shunsuke Okada, Tomonori Aoyama, Tatsunori Isogai, Masaki Noguchi
  • Publication number: 20220415920
    Abstract: According to one embodiment, a semiconductor memory device includes a circuitry layer, first conductive layers, a pillar layer, and a second conductive layer. The circuitry layer is provided on a substrate and includes a CMOS circuit. The first conductive layers are provided above the circuitry layer, and are stacked with an insulation layer interposed therebetween. The pillar layer crosses the first conductive layers, and includes silicon single crystal. The second conductive layer is provided on the pillar layer and includes silicon single crystal containing impurities. The first conductive layers are provided between the circuitry layer and the second conductive layer.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Applicant: Kioxia Corporation
    Inventors: Shuto YAMASAKA, Tomonori AOYAMA
  • Publication number: 20220013539
    Abstract: In one embodiment, a semiconductor device includes a stacked film including a plurality of electrode layers and a plurality of insulating layers alternately stacked in a first direction. The device further includes a columnar portion including a charge storage layer and a first semiconductor layer extending through the stacked film in the first direction, the first semiconductor layer including an impurity element. The device further includes a second semiconductor layer or a first insulator provided on the stacked film and the columnar portion, the second semiconductor layer or the first insulator including the impurity element and having a concentration gradient of the impurity element in the first direction.
    Type: Application
    Filed: March 16, 2021
    Publication date: January 13, 2022
    Applicant: Kioxia Corporation
    Inventors: Tatsunori ISOGAI, Shunsuke OKADA, Tomonori AOYAMA, Masaki NOGUCHI
  • Patent number: 11139378
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, a charge storage layer provided on the surface of the semiconductor layer via a first insulating film, and an electrode layer provided on the surface of the charge storage layer via a second insulating film. The first insulating film includes a first region where the compositional ratio of nitrogen to silicon, oxygen and nitrogen varies from a first value to a second value, which is lower than the first value, along a first direction from the semiconductor layer toward the charge storage layer.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 5, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaki Noguchi, Tatsunori Isogai, Tomonori Aoyama
  • Publication number: 20210296458
    Abstract: A semiconductor storage device relating to one embodiment includes: a stacked body in which electrode films and insulating films are alternately stacked in a first direction; a first and a second charge storage films that are arranged away from each other in the first direction inside the stacked body and each face one of the electrode films; and a tunnel insulating film that extends in the first direction inside the stacked body and is in contact with the first and the second charge storage films. The first and the second charge storage films each include a first film that is in contact with the electrode film and contains a High-k material, and a second film that is provided between the first film and the tunnel insulating film and contains silicon nitride.
    Type: Application
    Filed: December 14, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Shunsuke OKADA, Tomonori AOYAMA, Tatsunori ISOGAI, Masaki NOGUCHI
  • Publication number: 20200295201
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, a charge storage layer provided on the surface of the semiconductor layer via a first insulating film, and an electrode layer provided on the surface of the charge storage layer via a second insulating film. The first insulating film includes a first region where the compositional ratio of nitrogen to silicon, oxygen and nitrogen varies from a first value to a second value, which is lower than the first value, along a first direction from the semiconductor layer toward the charge storage layer.
    Type: Application
    Filed: August 29, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masaki NOGUCHI, Tatsunori ISOGAI, Tomonori AOYAMA
  • Patent number: 10741383
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes alternately forming a plurality of first films and a plurality of second films on a substrate, and forming an opening in the first and second films. The method further includes sequentially forming a first insulator, a charge storage layer, a second insulator and a semiconductor layer on surfaces of the first and second films in the opening. The second insulator includes a silicon oxynitride film, and the silicon oxynitride film is formed using a first gas that includes silicon and a first element, a second gas that includes oxygen and nitrogen, and a third gas that includes a second element that reacts with the first element.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaki Noguchi, Tatsunori Isogai, Tomonori Aoyama
  • Publication number: 20190296041
    Abstract: According to one embodiment, a semiconductor memory device includes a circuitry layer, first conductive layers, a pillar layer, and a second conductive layer. The circuitry layer is provided on a substrate and includes a CMOS circuit. The first conductive layers are provided above the circuitry layer, and are stacked with an insulation layer interposed therebetween. The pillar layer crosses the first conductive layers, and includes silicon single crystal. The second conductive layer is provided on the pillar layer and includes silicon single crystal containing impurities. The first conductive layers are provided between the circuitry layer and the second conductive layer.
    Type: Application
    Filed: September 6, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shuto YAMASAKA, Tomonori AOYAMA
  • Patent number: 10403642
    Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Matsuo, Akiko Sekihara, Akira Takashima, Tomonori Aoyama, Tatsunori Isogai, Masaki Noguchi
  • Publication number: 20190164742
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes alternately forming a plurality of first films and a plurality of second films on a substrate, and forming an opening in the first and second films. The method further includes sequentially forming a first insulator, a charge storage layer, a second insulator and a semiconductor layer on surfaces of the first and second films in the opening. The second insulator includes a silicon oxynitride film, and the silicon oxynitride film is formed using a first gas that includes silicon and a first element, a second gas that includes oxygen and nitrogen, and a third gas that includes a second element that reacts with the first element.
    Type: Application
    Filed: September 6, 2018
    Publication date: May 30, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masaki NOGUCHI, Tatsunori ISOGAI, Tomonori AOYAMA
  • Publication number: 20190139981
    Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.
    Type: Application
    Filed: August 7, 2018
    Publication date: May 9, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Matsuo, Akiko Sekihara, Akira Takashima, Tomonori Aoyama, Tatsunori Isogai, Masaki Noguchi
  • Patent number: 9532409
    Abstract: In accordance with an embodiment, a microwave irradiation apparatus includes a chamber and a polarizing plate. The chamber is configured to accommodate a substrate and is provided with an introduction port to introduce the microwave applied to the substrate from a direction at an angle within a range of ±45 degrees to a direction horizontal to a surface of the substrate. The polarizing plate is installed between the introduction port and the substrate, and selectively transmits a microwave where an amplitude direction of a magnetic field or an electric field is vertical to the surface of the substrate.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomonori Aoyama
  • Publication number: 20160365353
    Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes forming a first film on an inner wall of a hole in a stack on a substrate, forming a polycrystalline silicon film on the first film, and conducting a thermal annealing treatment in an atmosphere of ozone or oxygen radical to reduce defects in an interface between the first film and the polycrystalline silicon film. In the stack second films and third films are repeatedly stacked on the substrate in this order more than once.
    Type: Application
    Filed: January 27, 2016
    Publication date: December 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tomonori AOYAMA
  • Patent number: 9466517
    Abstract: According to one embodiment, a microwave annealing apparatus is provided, including a housing shielding electromagnetic waves, a first electromagnetic wave source configured to apply a first electromagnetic wave into the housing, a second electromagnetic wave source configured to apply, into the housing, a second electromagnetic wave having a higher frequency than the first electromagnetic wave, a susceptor configured to hold a semiconductor substrate, made of a material transparent to the first electromagnetic wave and provided in the housing, a temperature measuring device configured to measure the temperature of the semiconductor substrate, and a control unit configured to control the power of each of the first and second electromagnetic wave sources in accordance with the temperature measured by the temperature measuring device.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: October 11, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ohno, Tomonori Aoyama, Kiyotaka Miyano, Yoshinori Honguh, Masataka Shiratsuchi
  • Patent number: 9449848
    Abstract: According to one embodiment, the manufacturing method for the semiconductor device according to the embodiment includes carrying out ion implantation to the semiconductor layer and forming an amorphous layer on the surface of the semiconductor layer, and a heat treatment process using microwave annealing at a temperature higher than or equal to 200° C. and lower than or equal to 700° C. and single crystallizes the amorphous layer.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: September 20, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaka Miyano, Wakana Kai, Tatsunori Isogai, Tomonori Aoyama
  • Publication number: 20160268283
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers; a first electrode layer included in the plurality of electrode layers; a second electrode layer included in the plurality of electrode layers; a first insulating layer provided between the first electrode layer and the second electrode layer, and provided in contact with the first electrode layer and the second electrode layer; a semiconductor portion; a charge storage film; a first conductive film; and second conductive film. The first conductive film is provided between the first electrode layer and the charge storage film, and provided in contact with the first insulating layer. The second conductive film is provided between the second electrode layer and the charge storage film, and provided in contact with the first insulating layer.
    Type: Application
    Filed: July 9, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KITAMURA, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Junichi Wada, Kei Watanabe, Shinya Okuda, Hirotaka Ogihara, Hiroshi Nakazawa, Tomonori Aoyama, Kenji Aoyama, Hideaki Aochi