Patents by Inventor Tomonori Fujimoto
Tomonori Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7158424Abstract: In order to decrease the circuit scale of a power supply circuit and the area occupied by the power supply circuit over a semiconductor substrate, the power supply circuit, which supplies a supply voltage to respective parts of a memory circuit, includes a word driver power supply (first power supply circuit), a sense amplifier power supply (second power supply circuit), a bit line precharge power supply, a cell plate power supply, a substrate bias power supply, and a word line bias power supply. The word driver power supply supplies a word driver with a voltage generated by directly increasing an external supply voltage, whereas the other power supplies (e.g., the sense amplifier power supply) supply a sense amplifier, etc., with a voltage generated by decreasing the external supply voltage.Type: GrantFiled: December 8, 2004Date of Patent: January 2, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidefumi Ohtsuka, Kiyoto Ohta, Tomonori Fujimoto
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Patent number: 7136312Abstract: In a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.Type: GrantFiled: August 16, 2004Date of Patent: November 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Hirohito Kikukawa
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Patent number: 7038967Abstract: A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.Type: GrantFiled: June 10, 2004Date of Patent: May 2, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshitaka Uchikoba, Tomonori Fujimoto, Kiyoto Ohta
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Patent number: 6999368Abstract: A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.Type: GrantFiled: May 18, 2004Date of Patent: February 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Hirohito Kikukawa
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Publication number: 20050128786Abstract: In order to decrease the circuit scale of a power supply circuit and the area occupied by the power supply circuit over a semiconductor substrate, the power supply circuit, which supplies a supply voltage to respective parts of a memory circuit, includes a word driver power supply (first power supply circuit), a sense amplifier power supply (second power supply circuit), a bit line precharge power supply, a cell plate power supply, a substrate bias power supply, and a word line bias power supply. The word driver power supply supplies a word driver with a voltage generated by directly increasing an external supply voltage, whereas the other power supplies (e.g., the sense amplifier power supply) supply a sense amplifier, etc., with a voltage generated by decreasing the external supply voltage.Type: ApplicationFiled: December 8, 2004Publication date: June 16, 2005Inventors: Hidefumi Ohtsuka, Kiyoto Ohta, Tomonori Fujimoto
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Publication number: 20050057987Abstract: According to the invention, in a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.Type: ApplicationFiled: August 16, 2004Publication date: March 17, 2005Inventors: Tomonori Fujimoto, Kiyoto Ohta, Hirohito Kikukawa
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Publication number: 20050052923Abstract: A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.Type: ApplicationFiled: June 10, 2004Publication date: March 10, 2005Inventors: Toshitaka Uchikoba, Tomonori Fujimoto, Kiyoto Ohta
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Patent number: 6864693Abstract: A semiconductor integrated circuit is provided in which a negative voltage generation circuit capable of supplying a memory cell transistor substrate with a stable negative voltage, independently of the fluctuation of a power source voltage or environmental conditions and the process conditions etc., is realized easily, and in which the data holding time of a memory can be secured sufficiently, and the power consumption is reduced.Type: GrantFiled: May 10, 2001Date of Patent: March 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kondo, Kiyoto Ohta, Tomonori Fujimoto
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Publication number: 20040240299Abstract: A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.Type: ApplicationFiled: May 18, 2004Publication date: December 2, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Hirohito Kikukawa
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Patent number: 6785187Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.Type: GrantFiled: December 23, 2002Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Shoji Sakamoto, Kiyoto Ohta
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Patent number: 6654299Abstract: A semiconductor integrated circuit includes a plurality of semiconductor memory devices implemented as DRAMs and an output selector on the same chip. External terminals of the chip include: terminals for inputting an inverted row address strobe signal /RAS to the respective semiconductor memory devices individually; and common terminals for inputting PRAUT, SLF, /CAS, ADR, /WE, /OE, CLK and TMODE signals to all the memory devices. The output signals TDQ, SRAS, MOUT and BITST of the semiconductor memory devices are controlled by the output selector, passed through a common test bus and then output from a common external terminal.Type: GrantFiled: August 6, 2001Date of Patent: November 25, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidefumi Otsuka, Tomonori Fujimoto
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Patent number: 6628555Abstract: A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.Type: GrantFiled: August 15, 2002Date of Patent: September 30, 2003Assignee: Matsushita Electric Industrial Co. Ltd.Inventors: Masataka Kondo, Kiyoto Oota, Tomonori Fujimoto, Yoshihiko Sumimoto
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Patent number: 6621753Abstract: A semiconductor device capable of refreshing a plurality of memory cells. In operation, when requesting a data read operation a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. The sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation.Type: GrantFiled: December 20, 2002Date of Patent: September 16, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Yuji Yamasaki
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Patent number: 6570802Abstract: A semiconductor memory device including a memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to an output signal from the timer circuit. The first internal address generation circuit generates a refresh address of the entire memory region, and the second internal address generation circuit generates a refresh address of a certain part of the regions. By carrying out refresh of only a part of the memory required to be retained, the electric power consumption can be reduced.Type: GrantFiled: November 13, 2001Date of Patent: May 27, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidefumi Ohtsuka, Yuji Yamasaki, Tomonori Fujimoto
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Publication number: 20030086320Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.Type: ApplicationFiled: December 23, 2002Publication date: May 8, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Shoji Sakamoto, Kiyoto Ohta
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Publication number: 20030086319Abstract: When a data read operation is requested, for example, a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated as sense amplifiers start amplifying data of corresponding memory cells. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. Moreover, the sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation. Thus, it is no longer necessary to perform an auto refresh operation.Type: ApplicationFiled: December 20, 2002Publication date: May 8, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Yuji Yamasaki
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Patent number: 6532187Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.Type: GrantFiled: May 31, 2001Date of Patent: March 11, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Shoji Sakamoto, Kiyoto Ohta
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Patent number: 6507529Abstract: A semiconductor device capable of refreshing a plurality of memory cells. In operation, when requesting a data read operation a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. The sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation.Type: GrantFiled: December 6, 2001Date of Patent: January 14, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Yuji Yamasaki
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Publication number: 20020191447Abstract: To provide a boosting circuit that is included in a semiconductor integrated circuit in order for stabilizing a boosted potential with high efficiency. Therefore, the present invention is provided with a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.Type: ApplicationFiled: August 15, 2002Publication date: December 19, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kondo, Kiyoto Oota, Tomonori Fujimoto, Yoshihiko Sumimoto
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Patent number: 6459643Abstract: A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.Type: GrantFiled: February 28, 2001Date of Patent: October 1, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kondo, Kiyoto Oota, Tomonori Fujimoto, Yoshihiko Sumimoto