Patents by Inventor Tomonori Kajino

Tomonori Kajino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984484
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: May 14, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomonori Kajino, Taichi Iwasaki, Tatsuya Fujishima, Masayuki Shishido, Nozomi Kido
  • Publication number: 20220310808
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.
    Type: Application
    Filed: September 9, 2021
    Publication date: September 29, 2022
    Applicant: Kioxia Corporation
    Inventors: Tomonori KAJINO, Taichi IWASAKI, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Nozomi KIDO
  • Patent number: 10777574
    Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki Shishido, Tatsuya Fujishima, Nozomi Kido, Tomonori Kajino
  • Patent number: 10748915
    Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Nojima, Megumi Shibata, Tomonori Kajino, Taro Shiokawa
  • Publication number: 20200091182
    Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.
    Type: Application
    Filed: March 12, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki SHISHIDO, Tatsuya FUJISHIMA, Nozomi KIDO, Tomonori KAJINO
  • Publication number: 20200066748
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of insulating layers and a plurality of conductive layers are alternately stacked above a substrate, a pillar that penetrates the stacked body while extending in a stacking direction of the stacked body, and a semiconductor layer, a first insulating layer, a charge accumulation layer, and a second insulating layer, which are stacked on a side surface of the pillar in order from the pillar, wherein the semiconductor layer has an average grain size that is larger on a side nearer to the pillar and is smaller on a side nearer to the first insulating layer.
    Type: Application
    Filed: December 4, 2018
    Publication date: February 27, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Daisuke MATSUSHITA, Yui KAGI, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Nozomi KIDO, Tomonori KAJINO, Nobuhito KUGE
  • Publication number: 20190081053
    Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.
    Type: Application
    Filed: March 1, 2018
    Publication date: March 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro NOJIMA, Megumi SHIBATA, Tomonori KAJINO, Taro SHIOKAWA
  • Patent number: 9056822
    Abstract: PAH is subjected to C—H/C—B coupling using a specific boron compound, a palladium compound, and o-chloranil to produce a compound in which a C—H bond of the PAH is directly arylated regioselectively in a simple manner. When the substrate and the boron compound are appropriately selected, a larger PAH can also be obtained by further performing an annulation reaction after the coupling reaction. Similarly, when PAH is subjected to C—H/C—H cross-coupling using a specific aromatic compound, a palladium compound, and o-chloranil, a compound in which a C—H bond of the PAH is directly arylated regioselectively can be produced in a simple manner. When the substrate and the aromatic compound are appropriately selected in this case, a larger PAH can also be obtained by further performing an annulation reaction after the cross-coupling reaction.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: June 16, 2015
    Assignee: National University Corporation Nagoya University
    Inventors: Kenichiro Itami, Kenji Mochida, Katsuaki Kawasumi, Yasutomo Segawa, Tomonori Kajino
  • Publication number: 20140206908
    Abstract: PAH is subjected to C—H/C—B coupling using a specific boron compound, a palladium compound, and o-chloranil to produce a compound in which a C—H bond of the PAH is directly arylated regioselectively in a simple manner. When the substrate and the boron compound are appropriately selected, a larger PAH can also be obtained by further performing an annulation reaction after the coupling reaction. Similarly, when PAH is subjected to C—H/C—H cross-coupling using a specific aromatic compound, a palladium compound, and o-chloranil, a compound in which a C—H bond of the PAH is directly arylated regioselectively can be produced in a simple manner. When the substrate and the aromatic compound are appropriately selected in this case, a larger PAH can also be obtained by further performing an annulation reaction after the cross-coupling reaction.
    Type: Application
    Filed: June 8, 2012
    Publication date: July 24, 2014
    Applicant: NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY
    Inventors: Kenichiro Itami, Kenji Mochida, Katsuaki Kawasumi, Yasutomo Segawa, Tomonori Kajino