Patents by Inventor Tomonori Okudaira
Tomonori Okudaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9503018Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: GrantFiled: November 17, 2015Date of Patent: November 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Publication number: 20160142011Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: ApplicationFiled: November 17, 2015Publication date: May 19, 2016Inventors: Toshiaki TSUTSUMI, Yoshihiro FUNATO, Tomonori OKUDAIRA, Tadato YAMAGATA, Akihisa UCHIDA, Takeshi TERASAKI, Tomohisa SUZUKI, Yoshiharu KANEGAE
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Patent number: 9252793Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: GrantFiled: November 29, 2010Date of Patent: February 2, 2016Assignee: Renesas Electronics CorporationInventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Publication number: 20130314165Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: ApplicationFiled: November 29, 2010Publication date: November 28, 2013Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Patent number: 8338247Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.Type: GrantFiled: March 9, 2010Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Tadashi Yamaguchi, Toshiaki Tsutsumi, Satoshi Ogino, Kazumasa Yonekura, Kenji Kawai, Yoshihiro Miyagawa, Tomonori Okudaira, Keiichiro Kashihara, Kotaro Kihara
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Patent number: 8148248Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.Type: GrantFiled: March 22, 2011Date of Patent: April 3, 2012Assignee: Renesas Electronics CorporationInventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
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Patent number: 8022445Abstract: A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation <100> of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.Type: GrantFiled: July 27, 2009Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Tadashi Yamaguchi, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
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Publication number: 20110207317Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.Type: ApplicationFiled: March 22, 2011Publication date: August 25, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
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Patent number: 7936016Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.Type: GrantFiled: March 30, 2009Date of Patent: May 3, 2011Assignee: Renesas Electronics CorporationInventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
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Publication number: 20110037103Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a plurality of p-channel type MISFETs for logic, a plurality of n-channel type MISFETs for logic, a plurality of p-channel type MISFETs for memory, and a plurality of n-channel type MISFETs for memory are mixedly mounted. At least a part of the p-channel type MISFETs for logic have each a source/drain region constituted by silicon-germanium, and all the n-channel type MISFETs for logic have each a source/drain region constituted by silicon. All the p-channel type MISFETs for memory have each a source/drain region constituted by silicon, and all the n-channel type MISFETs for memory have each a source/drain region constituted by silicon.Type: ApplicationFiled: August 6, 2010Publication date: February 17, 2011Inventors: Tadashi YAMAGUCHI, Keiichiro KASHIHARA, Toshiaki TSUTSUMI, Tomonori OKUDAIRA, Kotaro KIHARA
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Patent number: 7872314Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.Type: GrantFiled: March 19, 2010Date of Patent: January 18, 2011Assignee: Renesas Electronics CorporationInventors: Tadashi Yamaguchi, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
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Publication number: 20100230761Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.Type: ApplicationFiled: March 9, 2010Publication date: September 16, 2010Inventors: Tadashi Yamaguchi, Toshiaki Tsutsumi, Satoshi Ogino, Kazumasa Yonekura, Kenji Kawai, Yoshihiro Miyagawa, Tomonori Okudaira, Keiichiro Kashihara, Kotaro Kihara
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Publication number: 20100171183Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.Type: ApplicationFiled: March 19, 2010Publication date: July 8, 2010Applicant: Renesas Technology Corp.Inventors: Tadashi YAMAGUCHI, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
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Patent number: 7696050Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.Type: GrantFiled: September 29, 2006Date of Patent: April 13, 2010Assignee: Renesas Technology Corp.Inventors: Tadashi Yamaguchi, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
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Publication number: 20090291537Abstract: A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation <100> of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.Type: ApplicationFiled: July 27, 2009Publication date: November 26, 2009Applicant: Renesas Technology Corp.Inventors: Tadashi YAMAGUCHI, Keiichiro KASHIHARA, Tomonori OKUDAIRA, Toshiaki TSUTSUMI
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Publication number: 20090283909Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.Type: ApplicationFiled: March 30, 2009Publication date: November 19, 2009Inventors: Toshiaki TSUTSUMI, Tomonori OKUDAIRA, Keiichiro KASHIHARA, Tadashi TAMAGUCHI
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Patent number: 7517800Abstract: A manufacturing method of a semiconductor device including a TiN film, including a deposition step of forming a TiN film by the CVD method, an anneal step of performing a heat treatment to the formed TiN film in an atmosphere of NH3 gas, an NH3 gas purge step of purging NH3 gas, and a step of further repeating the deposition step, the anneal step, and the NH3 gas purge step for at least one time. The deposition step is performed using titanium halide gas and NH3 gas as material gases and with a deposition temperature of 300° C.-450° C. to form the TiN film by a thickness of 1 nm-5 nm for each deposition step. Thus, a semiconductor device in which generation of irregularly grown objects in the TiN film is suppressed and a manufacturing method thereof can be provided.Type: GrantFiled: January 13, 2005Date of Patent: April 14, 2009Assignees: Renesas Technology Corp., Tokyo Electron LimitedInventors: Tomonori Okudaira, Takeshi Hayashi, Hiroshi Fujiwara, Yasushi Fujita, Kiyoteru Kobayashi
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Publication number: 20090079007Abstract: The present invention can prevent occurrence of an off-leak current in the NMISFETs formed over the Si (110) substrate and having a silicided source/drain region. The semiconductor device includes N channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) which are formed over a semiconductor substrate having a main surface with a (110) plane orientation and have a source region and a drain region at least one of which has thereover nickel silicide or a nickel alloy silicide. Of these NMISFETs, those having a channel width less than 400 nm are laid out so that their channel length direction is parallel to a <100> crystal orientation.Type: ApplicationFiled: September 17, 2008Publication date: March 26, 2009Inventors: TADASHI YAMAGUCHI, Keiichiro Kashihara, Toshiaki Tsutsumi, Tomonori Okudaira
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Publication number: 20080121950Abstract: Even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is realized. The channel length direction of n channel MISFET where the silicide region of nickel or a nickel alloy was formed on the source and the drain is arranged so that it may become parallel to the crystal orientation <100> of a semiconductor substrate. Since it is hard to extend the silicide region of nickel or a nickel alloy in the direction of crystal orientation <100>, even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is obtained.Type: ApplicationFiled: June 29, 2007Publication date: May 29, 2008Applicant: Renesas Technology Corp.Inventors: Tadashi YAMAGUCHI, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
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Publication number: 20070284671Abstract: Gate electrodes made of polysilicon film are isolated and face each other by way of a side wall spacer portion that fills a gap formed above an isolation insulating film at the boundary of NMIS region and PMIS region. A first metal film is formed on one of the gate electrodes, and an inhomogeneous second metal film is formed on the other of the gate electrodes. The both gate electrodes become inhomogeneous metal silicide gates through the promotion of silicide reaction by heat treatment. The mutual diffusion of metal atoms from the metal film to the gate electrode is suppressed by the interposition of the side wall spacer portion being an insulating film.Type: ApplicationFiled: June 7, 2007Publication date: December 13, 2007Applicant: Renesas Technology Corp.Inventors: Toshiaki TSUTSUMI, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi