Abstract: A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.

Abstract: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

Abstract: A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as failure information in a failure information storage register. The circuit includes a storage determining circuit determining whether or not to store the failure information in a failure information storage register based on preset failure information storage method information.

Abstract: A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.

Abstract: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

Abstract: A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as failure information in a failure information storage register. The circuit includes a storage determining circuit determining whether or not to store the failure information in a failure information storage register based on preset failure information storage method information.