Abstract: An image forming apparatus includes a rotatable image bearing member and a rotatable developing member to carry developer made up of toner particles and carrier particles adhered to surfaces of the toner particles. Where a pressing force pressing the developing member against the image bearing member is F1, a total number of the carrier particles interposed between the toner particles and the image bearing member is N1, and an adhesion Ft between a carrier particle and a toner particle, measured when the carrier particle is pressed against the toner particle with F1/N1 that is a pressing force per unit carrier particle, and an adhesion Fdr1 between the carrier particle and the image bearing member, measured when the carrier particle is pressed against the image bearing member with F1/N1, satisfy Ft?Fdr1.

Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller controls the nonvolatile memory, writes data to a random access memory in a host, and reads data from the random access memory. The random access memory includes regions in first units to which the controller is accessible. The controller uses encryption keys associated with the regions, respectively, for encrypting data to be written into each of the regions and decrypting data read from each of the regions.

Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: A storage device includes a memory, a write circuit, a read circuit, and a debug information register. The memory includes a data area and a redundant area that corresponds to the data area. The write circuit writes first data specified in a write command to the data area, and first information about a transmission source which has transmitted the write command, to the redundant area. The read circuit reads the first data as second data from the data area, and reads the first information as second information from the redundant area, in response to a read command. The debug information register stores the second information read by the read circuit.

Abstract: A storage device includes a memory, a write circuit, a read circuit, and a debug information register. The memory includes a data area and a redundant area that corresponds to the data area. The write circuit writes first data specified in a write command to the data area, and first information about a transmission source which has transmitted the write command, to the redundant area. The read circuit reads the first data as second data from the data area, and reads the first information as second information from the redundant area, in response to a read command. The debug information register stores the second information read by the read circuit.

Abstract: A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.

Abstract: A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller controls the nonvolatile memory, writes data to a random access memory in a host, and reads data from the random access memory. The random access memory includes regions in first units to which the controller is accessible. The controller uses encryption keys associated with the regions, respectively, for encrypting data to be written into each of the regions and decrypting data read from each of the regions.

Abstract: A memory system includes: a non-volatile first memory; a second memory which is a set-associative cache memory including a plurality of ways; and a memory controller The first memory stores a plurality of pieces of first information each of which associates a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory. The plurality of pieces of first information includes second information and third information. The second information associates a logical address with a physical address in a first unit. The third information associates a logical address with a physical address in a second unit different from the first unit. The memory controller caches the second information only in a first way. The memory controller caches the third information only in a second way different from the first way.

Abstract: There is provided an irradiation device including an irradiation unit configured to emit light, and an irradiation control unit configured to switch irradiation regions irradiated with the light by the irradiation unit according to a synchronization signal for controlling an exposure period of a pixel of an imaging device of an imaging unit.

Abstract: There is provided an irradiation device including an irradiation unit configured to emit light, and an irradiation control unit configured to switch irradiation regions irradiated with the light by the irradiation unit according to a synchronization signal for controlling an exposure period of a pixel of an imaging device of an imaging unit.

Abstract: Disclosed herein is an image processing apparatus including an input section, a bus, a memory interface, an output section, and a control section.

Abstract: A medicine containing, as an active ingredient, a cyclic amine derivative represented by the following formula (I), a pharmaceutically acceptable acid addition salt thereof or a pharmaceutically acceptable C1 to C6 alkyl addition salt thereof. The medicine has an action for treating or preventing diseases in which CCR3 participates, such as asthma and allergic rhinitis.

Abstract: Disclosed herein is an image processing apparatus including an input section, a bus, a memory interface, an output section, and a control section.

Abstract: The invention provides low molecular compounds having activity which inhibits binding of CCR3 ligands to CCR3 on target cells, i.e. CCR3 antagonists. The invention also provides 4,4-(disubstituted)piperidine derivatives represented by formula (I) below, pharmaceutically acceptable acid adducts thereof, or pharmaceutically acceptable C1-C6 alkyl adducts thereof, as well as pharmaceutical compositions comprising them as effective ingredients, which are useful for treatment or prevention of diseases associated with CCR3, such as asthma and allergic rhinitis.

Abstract: The invention provides low molecular compounds having activity which inhibits binding of CCR3 ligands to CCR3 on target cells, i.e. CCR3 antagonists. The invention also provides compounds represented by formula (I) below, pharmaceutically acceptable acid adducts thereof, or pharmaceutically acceptable C1-C6 alkyl adducts thereof, as well as pharmaceutical compositions comprising them as effective ingredients, which are useful for treatment or prevention of diseases associated with CCR3, such as asthma and allergic rhinitis.

Abstract: Remedies or prophylactics for diseases in association with CCR5 such as AIDS, rheumatoid arthritis or nephritis comprising a cyclic amine compound represented by the following formula (I), a pharmaceutically acceptable acid addition salt thereof or a pharmaceutically acceptable C1-C6 alkyl addition salt thereof, as an active ingredient.

Abstract: The invention provides low molecular compounds having activity which inhibits binding of CCR3 ligands to CCR3 on target cells, i.e. CCR3 antagonists. The invention also provides 4,4-(disubstituted)piperidine derivatives represented by formula (I) below, pharmaceutically acceptable acid adducts thereof, or pharmaceutically acceptable C1-C6 alkyl adducts thereof, as well as pharmaceutical compositions comprising them as effective ingredients, which are useful for treatment or prevention of diseases associated with CCR3, such as asthma and allergic rhinitis.

Abstract: The invention provides low molecular compounds having activity which inhibits binding of CCR3 ligands to CCR3 on target cells, i.e. CCR3 antagonists. The invention also provides compounds represented by formula (I) below, pharmaceutically acceptable acid adducts thereof, or pharmaceutically acceptable C1-C6 alkyl adducts thereof, as well as pharmaceutical compositions comprising them as effective ingredients, which are useful for treatment or prevention of diseases associated with CCR3, such as asthma and allergic rhinitis.