Patents by Inventor Tomoo Hamada
Tomoo Hamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8418157Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.Type: GrantFiled: February 16, 2010Date of Patent: April 9, 2013Assignee: Panasonic CorporationInventors: Hajime Ogawa, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
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Publication number: 20100199269Abstract: A program optimization device which, when optimizing a program, performs optimization depending on characteristics of data to be processed by the program without having to execute the program before the optimization, includes: an intermediate code conversion unit that converts an input program to be optimized, into an intermediate code; a variable value setting unit that sets a possible value of a variable according to externally provided information; a node value calculation unit that calculates a possible value of a node included in the intermediate code according to the value set by the variable value setting unit; an intermediate code optimization unit that optimizes the intermediate code according to the value calculated by the node value calculation unit; and an output program conversion unit that converts the intermediate code optimized by the intermediate code optimization unit, to an output program.Type: ApplicationFiled: October 8, 2008Publication date: August 5, 2010Applicant: PANASONIC CORPORATIONInventors: Dai Hattori, Tomoo Hamada
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Publication number: 20100175056Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.Type: ApplicationFiled: February 16, 2010Publication date: July 8, 2010Inventors: Hajime OGAWA, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
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Patent number: 7698696Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.Type: GrantFiled: June 30, 2003Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Hajime Ogawa, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
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Publication number: 20090199168Abstract: A program conversion method that can increase variations of applicable optimizations and effects of the optimization, by being provided with characteristics of a variable or an association between two or more variables as hint information for optimization by a programmer or profiler. The program conversion method converts a source program in a computer and includes: obtaining a constraint equation including at least one of a variable in the source program, a constant, an operator, a pseudo variable, and a built-in function and producing a truth-value; and converting the source program by optimizing the constraint.Type: ApplicationFiled: February 5, 2009Publication date: August 6, 2009Applicant: Panasonic CorporationInventors: Tomoo HAMADA, Dai HATTORI
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Patent number: 7350165Abstract: A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.Type: GrantFiled: March 24, 2005Date of Patent: March 25, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryoko Miyachi, Tomoo Hamada, Hajime Ogawa, Shohei Michimoto, Yasuhiro Yamamoto, Teruo Kawabata, Hirotetsu Tomita
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Publication number: 20060212440Abstract: In a development of system software, a compiler system and the like are included in a program development system for increasing performance efficiency of an overall computer system and reducing manpower necessary for developing system software. The compiler system is a program for reading a source program and system level hint information and translating them into a machine language program, generating the machine language program and outputting task information that is information relating to the program. The system level hint information is a collection of information that become hints for optimization performed in the compiler system, and is made up of an analysis result obtained by a profiler, an instruction from a programmer, task information relating to the source program and task information relating to another source program that is different from the source program.Type: ApplicationFiled: March 9, 2006Publication date: September 21, 2006Applicant: Matsushita Electric Industrial Co., LtdInventors: Taketo Heishi, Tomoo Hamada
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Publication number: 20060150135Abstract: Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit.Type: ApplicationFiled: December 1, 2005Publication date: July 6, 2006Inventors: Tomoo Hamada, Hajime Ogawa, Ryoko Miyachi, Shohei Michimoto, Yasuhiro Yamamoto, Teruo Kawabata, Hirotetsu Tomita
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Publication number: 20060107267Abstract: An instruction scheduling method according to the present invention allocates each instruction included in an instruction sequence to be synthesized as a circuit to one of execution cycles in the circuit, and includes: detecting a freedom of each instruction, the freedom representing a time period within which the instruction can be allocated; calculating a load of a processing element corresponding to the instruction for each of the execution cycles; and allocating the instructions using the same processing element within the freedoms to different execution cycles based on the load.Type: ApplicationFiled: November 10, 2005Publication date: May 18, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Ryoko Miyachi, Hajime Ogawa, Tomoo Hamada, Teruo Kawabata
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Publication number: 20050216869Abstract: A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.Type: ApplicationFiled: March 24, 2005Publication date: September 29, 2005Inventors: Ryoko Miyachi, Tomoo Hamada, Hajime Ogawa, Shohei Michimoto, Yasuhiro Yamamoto, Teruo Kawabata, Hirotetsu Tomita
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Publication number: 20040098713Abstract: The present invention provides a highly-flexible compiler that a user can control optimization by the compiler precisely.Type: ApplicationFiled: June 30, 2003Publication date: May 20, 2004Inventors: Hajime Ogawa, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi