Patents by Inventor Tomoo Hishida

Tomoo Hishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory having memory cell regions and other regions alternately arranged along a bit line direction
    Patent number: 11974439
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: April 30, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • SEMICONDUCTOR MEMORY
    Publication number: 20230088310
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 23, 2023
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Semiconductor memory having first and second memory cell regions separated by a third region along a bit line direction
    Patent number: 11552095
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 10, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • SEMICONDUCTOR MEMORY DEVICE WITH A THREE-DIMENSIONAL STACKED MEMORY CELL STRUCTURE
    Publication number: 20210375923
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Application
    Filed: August 10, 2021
    Publication date: December 2, 2021
    Applicant: Kioxia Corporation
    Inventors: Tomoo HISHIDA, Yoshihisa IWATA
  • SEMICONDUCTOR MEMORY
    Publication number: 20210217755
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Semiconductor memory
    Patent number: 10971511
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • SEMICONDUCTOR MEMORY
    Publication number: 20200212053
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Semiconductor memory
    Patent number: 10622372
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20200091190
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Yoshihisa Iwata
  • Semiconductor memory device with a three-dimensional stacked memory cell structure
    Patent number: 10586806
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Yoshihisa Iwata
  • SEMICONDUCTOR MEMORY
    Publication number: 20190164979
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: January 30, 2019
    Publication date: May 30, 2019
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Semiconductor memory
    Patent number: 10199387
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • SEMICONDUCTOR MEMORY
    Publication number: 20180358368
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: August 17, 2018
    Publication date: December 13, 2018
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • SEMICONDUCTOR MEMORY DEVICE WITH A THREE-DIMENSIONAL STACKED MEMORY CELL STRUCTURE
    Publication number: 20180337194
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo HISHIDA, Yoshihisa IWATA
  • Semiconductor memory device with a three-dimensional stacked memory cell structure
    Patent number: 10068916
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Yoshihisa Iwata
  • Semiconductor memory
    Patent number: 10056403
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: August 21, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • SEMICONDUCTOR MEMORY
    Publication number: 20180006042
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Semiconductor memory
    Patent number: 9768188
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170104002
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoo HISHIDA, Yoshihisa IWATA
  • SEMICONDUCTOR MEMORY
    Publication number: 20170062441
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: November 11, 2016
    Publication date: March 2, 2017
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE