Abstract: A branch prediction control device, in an information processing unit which performs a pipeline process, generates a branch prediction address used for verification of an instruction being speculatively executed. The branch prediction control device includes a first return address storage unit storing the prediction return address, a second return address storage unit storing a return address to be generated depending on an execution result of the call instruction, and a branch prediction address storage unit sending a stored prediction return address as a branch prediction address and storing the sent branch prediction address. When the branch prediction address differs from a return address, which is generated after executing a branch instruction or a return instruction, contents stored in the second return address storage unit are copied to the first return address storage unit.

Abstract: A freeze forecasting device for a hot water heating apparatus, for forecasting a possibility of freeze of water in a water passage circuit due to reduction in outside air temperature at a forecast target time on a forecast target day. The device includes a clock portion; an outside air temperature sensor; an outside air temperature history storage portion; a retrieval portion for retrieving a past outside air temperature; and a forecasting portion for determining whether the retrieved past outside air temperature is not higher than a freezing critical temperature of the water in the water passage circuit and forecasting the possibility of freeze of the water in the water passage circuit at the forecast target time on the forecast target day.

Abstract: A branch prediction control device, in an information processing unit which performs a pipeline process, generates a branch prediction address used for verification of an instruction being speculatively executed. The branch prediction control device includes a first return address storage unit storing the prediction return address, a second return address storage unit storing a return address to be generated depending on an execution result of the call instruction, and a branch prediction address storage unit sending a stored prediction return address as a branch prediction address and storing the sent branch prediction address. When the branch prediction address differs from a return address, which is generated after executing a branch instruction or a return instruction, contents stored in the second return address storage unit are copied to the first return address storage unit.

Abstract: A freeze forecasting device for a hot water heating apparatus, for forecasting a possibility of freeze of water in a water passage circuit due to reduction in outside air temperature at a forecast target time on a forecast target day, the device comprising: a clock portion for automatically computing current year, month, day, and time; an outside air temperature sensor; an outside air temperature history storage portion for storing outside air temperatures for at least one year based on outputs from the clock portion and the outside air temperature sensor; a retrieval portion for retrieving a past outside air temperature in a time zone including a time identical to the forecast target time in a past year, month, and day corresponding to the year, month, and day of the forecast target day or a day before or after the forecast target day, from the outside air temperature history storage portion; and a forecasting portion for determining whether the retrieved past outside air temperature is not higher than a fre

Abstract: The invention provides a method of design for testability at RTL which can guarantee high fault coverage and a method of test sequence generation for easily generating test sequences for an RTL circuit which is designed to be easily testable by the method of design for testability. In the RTL circuit, scannable registers are selected so that the RTL circuit can attain an easily testable circuit structure such as an acyclic structure. This RTL circuit is timeframe expanded on the basis of a predetermined evaluation function and logically synthesized, so as to generate a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit, as a circuit for test sequence generation.

Abstract: A PLL jitter measuring method used for an integrated circuit with a PLL that generates an internal clock signal is disclosed, that comprises the steps of extracting jitter information of the internal clock signal of the PLL as an output signal to the outside of the integrated circuit without removing a package of the integrated circuit, and measuring the jitter of the internal clock signal with the extracted output signal.

Abstract: A power supply circuit of a semiconductor integrated circuit consuming a large load current at a low voltage has a source potential controller and a ground potential controller for stabilizing a supply voltage to the integrated circuit. The source potential controller controls the potential of the source line in the integrated circuit based on a reference source potential and a sensed potential of the source line. The ground potential controller controls the potential of the ground line in the integrated circuit based on a reference ground potential and a sensed potential of the ground line. Both the source potential controller and ground potential controller may be disposed outside or inside the integrated circuit.