Patents by Inventor Tomoo MINAKI
Tomoo MINAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210012749Abstract: A display driver includes gamma curve control circuitry and a converter controller. The gamma curve control circuitry is configured to generate a first gamma curve for a first display brightness value (DBV), and a second gamma curve for a second DBV lower than the first DBV. The converter controller is configured to control a digital-analog converter (DAC) configured to perform digital-analog conversion of an input image data. Further, the converter controller is configured to adjust an analog signal voltage amplitude of the DAC based on a range of an output voltage associated with the second gamma curve.Type: ApplicationFiled: September 21, 2020Publication date: January 14, 2021Inventors: Hirobumi FURIHATA, Kazutoshi AOGAKI, Tomoo MINAKI, Akio SUGIYAMA, Takashi NOSE
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Patent number: 10872552Abstract: A display driver comprises: subpixel rendering (SPR) circuitry configured to use, in SPR, predetermined regions which fall within two lines of input subpixels of an input image; buffer memory circuitry configured to store first subpixel data for a plurality of first subpixels of the input subpixels, wherein the plurality of the first subpixels each are encompassed in the predetermined regions; and a register configured to store coefficients, wherein the coefficients respectively correspond to shapes of the portions of the first subpixels encompassed in the predetermined regions. The SPR circuitry is configured to calculate second subpixel data for second subpixels of an output image, based on the first subpixel data stored in the buffer memory circuitry and the coefficients stored in the register.Type: GrantFiled: November 16, 2018Date of Patent: December 22, 2020Assignee: SYNAPTICS INCORPORATEDInventors: Tomoo Minaki, Hirobumi Furihata, Takashi Nose
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Publication number: 20200394975Abstract: A display driver comprises image processing circuitry and drive circuitry. The image processing circuitry is configured to output display image data representing a display image comprising an effective area to be displayed in a display area of a display panel and an invalid area not to be displayed in the display area. The drive circuitry drives the display panel based on the display image data comprising effective pixel data associated with first pixels included in the effective area and invalid pixel data associated with second pixels included in the invalid area. Effective pixel data associated with first pixels located within a boundary area adjacent to the invalid area is set to first grayscale values. The invalid pixel data associated with second pixels located within an insert area defined in the invalid area is set to second grayscale values comprising a value different from the first grayscale values.Type: ApplicationFiled: August 26, 2020Publication date: December 17, 2020Inventors: Tomoo MINAKI, Hirobumi FURIHATA, Takashi NOSE
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Publication number: 20200394980Abstract: A display driver is disclosed. The display driver includes: a memory that stores initial control points (CPs) defining a first gamma curve for a first analog state associated with a display panel (DP); CP calculation circuitry that generates, based on the initial CPs, calculated CPs for a second analog state associated with the DP; multiplexer circuitry that: inputs the calculated CPs, auxiliary CPs defining a second gamma curve, and a switching signal identifying a luminance of a region of an image; and outputs, based on the switching signal, selected CPs; and gamma curve calculation circuitry that: inputs a data value associated with the region of the image; generates, based on the selected CPs, a portion of an output gamma curve near the data value; and outputs a voltage data for displaying the region of the image on the DP based on the data value and the output gamma curve.Type: ApplicationFiled: November 15, 2018Publication date: December 17, 2020Applicant: Synaptics IncorporatedInventors: Hirobumi Furihata, Tomoo Minaki, Kazutoshi Aogaki, Takashi Nose
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Patent number: 10783850Abstract: A display driver includes gamma curve control circuitry and a converter controller. The gamma curve control circuitry is configured to generate a first gamma curve for a first display brightness value (DBV), and a second gamma curve for a second DBV lower than the first DBV. The converter controller is configured to control a digital-analog converter (DAC) configured to perform digital-analog conversion of an input image data. Further, the converter controller is configured to adjust an analog signal voltage amplitude of the DAC based on a range of an output voltage associated with the second gamma curve.Type: GrantFiled: October 31, 2018Date of Patent: September 22, 2020Assignee: SYNAPTICS INCORPORATEDInventors: Hirobumi Furihata, Kazutoshi Aogaki, Tomoo Minaki, Akio Sugiyama, Takashi Nose
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Publication number: 20200279542Abstract: A display driver is disclosed. The display driver includes: a memory configured to store control points defining a curve associated with a display panel; and shape calculation circuitry configured to: determine, based on the control points, a first intersection point of the curve and a width of a first line associated with the display panel; and modify image data of an image based on the first intersection point.Type: ApplicationFiled: November 15, 2018Publication date: September 3, 2020Applicant: Synaptics IncorporatedInventors: Tomoo Minaki, Hirobumi Furihata, Takashi Nose
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Patent number: 10762860Abstract: A display driver comprises image processing circuitry and drive circuitry. The image processing circuitry is configured to output display image data representing a display image comprising an effective area to be displayed in a display area of a display panel and an invalid area not to be displayed in the display area. The drive circuitry drives the display panel based on the display image data comprising effective pixel data associated with first pixels included in the effective area and invalid pixel data associated with second pixels included in the invalid area. Effective pixel data associated with first pixels located within a boundary area adjacent to the invalid area is set to first grayscale values. The invalid pixel data associated with second pixels located within an insert area defined in the invalid area is set to second grayscale values comprising a value different from the first grayscale values.Type: GrantFiled: September 25, 2019Date of Patent: September 1, 2020Assignee: SYNAPTICS INCORPORATEDInventors: Tomoo Minaki, Hirobumi Furihata, Takashi Nose
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Publication number: 20200273395Abstract: A system and method for rendering subpixels comprising performing an eight-color halftoning process on the second image data to generate third image data which describe a grayscale value of each of an R subpixel, a G subpixel and a B subpixel of each pixel with one bit, generating the third image data by performing a dithering process on the second image data using a dither value selected from elements of the dither table, when the third image data associated with a pixel of interest of the display panel is generated, and driving the display panel in response to the third image data.Type: ApplicationFiled: May 12, 2020Publication date: August 27, 2020Applicants: Synaptics Japan GK, Synaptics Japan GKInventors: Hirobumi FURIHATA, Tomoo MINAKI
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Patent number: 10657873Abstract: A system and method for rendering subpixels comprising performing an eight-color halftoning process on the second image data to generate third image data which describe a grayscale value of each of an R subpixel, a G subpixel and a B subpixel of each pixel with one bit, generating the third image data by performing a dithering process on the second image data using a dither value selected from elements of the dither table, when the third image data associated with a pixel of interest of the display panel is generated, and driving the display panel in response to the third image data.Type: GrantFiled: January 11, 2018Date of Patent: May 19, 2020Assignee: Synaptics Japan GKInventors: Hirobumi Furihata, Tomoo Minaki
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Publication number: 20200118504Abstract: A display driver comprises image processing circuitry and drive circuitry. The image processing circuitry is configured to output display image data representing a display image comprising an effective area to be displayed in a display area of a display panel and an invalid area not to be displayed in the display area. The drive circuitry drives the display panel based on the display image data comprising effective pixel data associated with first pixels included in the effective area and invalid pixel data associated with second pixels included in the invalid area. Effective pixel data associated with first pixels located within a boundary area adjacent to the invalid area is set to first grayscale values. The invalid pixel data associated with second pixels located within an insert area defined in the invalid area is set to second grayscale values comprising a value different from the first grayscale values.Type: ApplicationFiled: September 25, 2019Publication date: April 16, 2020Inventors: Tomoo MINAKI, Hirobumi FURIHATA, Takashi NOSE
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Publication number: 20200005693Abstract: A system and method for generate mura correction data comprises obtaining brightness values of a pixel-existing area and a pixel-absent area of a display panel. Further, updated brightness values are generated by replacing the brightness value of the pixel-absent area with a suitable value. Mura correction data is generated using the updated brightness values. A display driver is configured with the mura correction data for updating a display device.Type: ApplicationFiled: June 25, 2019Publication date: January 2, 2020Inventors: Hirobumi FURIHATA, Kazutoshi AOGAKI, Tomoo MINAKI
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Patent number: 10305709Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.Type: GrantFiled: August 17, 2017Date of Patent: May 28, 2019Assignee: Synaptics Japan GKInventors: Yoshihiko Hori, Takefumi Seno, Keiichi Itoigawa, Jun Kurosawa, Takashi Tamura, Hideaki Kuwada, Kazuhiko Kanda, Tomoo Minaki
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Publication number: 20190156727Abstract: A display driver comprises: subpixel rendering (SPR) circuitry configured to use, in SPR, predetermined regions which fall within two lines of input subpixels of an input image; buffer memory circuitry configured to store first subpixel data for a plurality of first subpixels of the input subpixels, wherein the plurality of the first subpixels each are encompassed in the predetermined regions; and a register configured to store coefficients, wherein the coefficients respectively correspond to shapes of the portions of the first subpixels encompassed in the predetermined regions. The SPR circuitry is configured to calculate second subpixel data for second subpixels of an output image, based on the first subpixel data stored in the buffer memory circuitry and the coefficients stored in the register.Type: ApplicationFiled: November 16, 2018Publication date: May 23, 2019Inventors: Tomoo MINAKI, Hirobumi FURIHATA, Takashi NOSE
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Publication number: 20190130872Abstract: A display driver includes gamma curve control circuitry and a converter controller. The gamma curve control circuitry is configured to generate a first gamma curve for a first display brightness value (DBV), and a second gamma curve for a second DBV lower than the first DBV. The converter controller is configured to control a digital-analog converter (DAC) configured to perform digital-analog conversion of an input image data.Type: ApplicationFiled: October 31, 2018Publication date: May 2, 2019Inventors: Hirobumi Furihata, Kazutoshi Aogaki, Tomoo Minaki, Akio Sugiyama, Takashi Nose
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Publication number: 20180197454Abstract: A system and method for rendering subpixels comprising performing an eight-color halftoning process on the second image data to generate third image data which describe a grayscale value of each of an R subpixel, a G subpixel and a B subpixel of each pixel with one bit, generating the third image data by performing a dithering process on the second image data using a dither value selected from elements of the dither table, when the third image data associated with a pixel of interest of the display panel is generated, and driving the display panel in response to the third image data.Type: ApplicationFiled: January 11, 2018Publication date: July 12, 2018Inventors: Hirobumi FURIHATA, Tomoo MINAKI
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Publication number: 20180054336Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.Type: ApplicationFiled: August 17, 2017Publication date: February 22, 2018Inventors: Yoshihiko HORI, Takefumi SENO, Keiichi ITOIGAWA, Jun KUROSAWA, Takashi TAMURA, Hideaki KUWADA, Kazuhiko KANDA, Tomoo MINAKI