Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.

Abstract: A semiconductor device includes a vertical semiconductor element having a deep layer, a current dispersion layer, a base region, a high-concentration region, and a trench gate structure. The deep layer has multiple sections being apart to each other in one direction. The current dispersion layer is between adjacent two of the sections of the deep layer. The high-concentration region is on a portion of the base region. The trench gate structure includes a gate trench, a gate insulation film and a gate electrode. The current dispersion layer is at a bottom of the trench gate structure, and has an ion-implanted layer extending from a bottom portion of the gate trench to a bottom portion of the deep layer or a location below the bottom portion of the deep layer.

Abstract: A semiconductor device includes a semiconductor element configured to form an upper-lower arm circuit of a power conversion device. The semiconductor element includes a control electrode, a high-potential electrode and a low-potential electrode. A parasitic capacitance between the control electrode and the high-potential electrode changes according to a potential difference between the high-potential electrode and the low-potential electrode. A value of the parasitic capacitance at a time when the potential difference is equal to 80 percent of a breakdown voltage of the semiconductor element is defined as a first capacitance value. An arbitrary value of the parasitic capacitance at a time when the potential difference is in an inclusive range of 20 percent to 40 percent of the breakdown voltage is defined as a second capacitance value. The first capacitance value is larger than the second capacitance value.

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

Abstract: A semiconductor device includes a semiconductor chip formed using a silicon carbide and having electrodes on a first surface and a second surface opposite to the first surface, a terminal disposed adjacent to the first surface and connected to the electrode on the first surface through a bonding member, and a heat sink disposed adjacent to the second surface and connected to the electrode on the second surface through a bonding member. The first surface is a (0001) plane and a thickness direction of the semiconductor chip corresponds to a [0001] direction. Of the distances between the end portions of the semiconductor chip having a square two-dimensional shape and the end portions of the terminal having a rectangular two-dimensional shape, the shortest distance L1 in a [1-100] direction is shorter than the shortest distance L2 in a [11-20] direction.

Abstract: A semiconductor device includes: a first element formed of a first constituent as a main constituent; a second element formed of a second constituent as a main constituent; a heat sink on which the first element and the second element are disposed; a first connection layer electrically connecting the first element to the heat sink; a second connection layer electrically connecting the second element to the heat sink; and a mold resin covering and protecting the first element, the second element and the heat sink. Sizes of the first element and the second element are set so that an equivalent plastic strain increment of the first connection layer is greater than the second connection layer. Accordingly, in the semiconductor device including semiconductor elements formed of different constituents, the elements are thermally protected without providing a temperature detector to the semiconductor element formed of one of the constituents.

Abstract: A semiconductor device includes: a first element formed of a first constituent as a main constituent; a second element formed of a second constituent as a main constituent; a heat sink on which the first element and the second element are disposed; a first connection layer electrically connecting the first element to the heat sink; a second connection layer electrically connecting the second element to the heat sink; and a mold resin covering and protecting the first element, the second element and the heat sink. Sizes of the first element and the second element are set so that an equivalent plastic strain increment of the first connection layer is greater than the second connection layer. Accordingly, in the semiconductor device including semiconductor elements formed of different constituents, the elements are thermally protected without providing a temperature detector to the semiconductor element formed of one of the constituents.

Abstract: A semiconductor device includes a semiconductor chip formed using a silicon carbide and having electrodes on a first surface and a second surface opposite to the first surface, a terminal disposed adjacent to the first surface and connected to the electrode on the first surface through a bonding member, and a heat sink disposed adjacent to the second surface and connected to the electrode on the second surface through a bonding member. The first surface is a (0001) plane and a thickness direction of the semiconductor chip corresponds to a [0001] direction. Of the distances between the end portions of the semiconductor chip having a square two-dimensional shape and the end portions of the terminal having a rectangular two-dimensional shape, the shortest distance L1 in a [1-100] direction is shorter than the shortest distance L2 in a [11-20] direction.

Abstract: A silicon carbide semiconductor device includes a junction barrier Schottky diode including a substrate, a drift layer, an insulating film, a Schottky barrier diode, and a plurality of second conductivity type layers. The Schottky barrier diode includes a Schottky electrode and an ohmic electrode. A PN diode is configured by the plurality of second conductivity type layers and the drift layer, and the plurality of second conductivity type layers is formed in stripes only in a direction parallel to a rod-shaped stacking fault.

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

Abstract: A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface.

Abstract: A silicon carbide semiconductor device includes a junction barrier Schottky diode including a substrate, a drift layer, an insulating film, a Schottky barrier diode, and a plurality of second conductivity type layers. The Schottky barrier diode includes a Schottky electrode and an ohmic electrode. A PN diode is configured by the plurality of second conductivity type layers and the drift layer, and the plurality of second conductivity type layers is formed in stripes only in a direction parallel to a rod-shaped stacking fault.

Abstract: A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface.

Abstract: A method of manufacturing a semiconductor device includes forming a drift layer on a substrate; forming a base layer on the drift layer; forming a trench to penetrate the base layer and to reach the drift layer; rounding off a part of a shoulder corner and a part of a bottom corner of the trench; covering an inner wall of the trench with an organic film; implanting an impurity to a surface portion of the base layer; forming a source region by activating the implanted impurity; and removing the organic film after the source region is formed, in which the substrate, the drift layer, the base layer and the source region are made of silicon carbide, and the implanting and the activating of the impurity are performed under a condition that the trench is covered with the organic film.

Abstract: A method of manufacturing a semiconductor device includes forming a drift layer on a substrate; forming a base layer on the drift layer; forming a trench to penetrate the base layer and to reach the drift layer; rounding off a part of a shoulder corner and a part of a bottom corner of the trench; covering an inner wall of the trench with an organic film; implanting an impurity to a surface portion of the base layer; forming a source region by activating the implanted impurity; and removing the organic film after the source region is formed, in which the substrate, the drift layer, the base layer and the source region are made of silicon carbide, and the implanting and the activating of the impurity are performed under a condition that the trench is covered with the organic film.