Patents by Inventor Tomoo Murata

Tomoo Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12668855
    Abstract: A method with which Mg can be removed from aluminum alloy melt whose raw material is scrap or the like. Metal removal method includes processing step of forming molten salt layer in contact with aluminum alloy melt containing Mg which covers at least part of the surface of the aluminum alloy melt. This method allows Mg to be taken in from aluminum alloy melt to molten salt layer and removed. Molten salt layer contains specific halogen element that is one or more of Cl or Br and specific metal element that is one or more of Cu, Zn, or Mn. The specific metal element is supplied as an oxide of the specific metal element to the molten salt layer. At that time, the molten salt layer contains Mg. The step of removing Mg is performed by disposing a conductor that bridges the aluminum alloy melt and the molten salt layer.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: June 30, 2026
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA TSUSHO CORPORATION
    Inventors: Takuma Minoura, Jun Yaokawa, Kazuma Hibi, Hiroshi Kawahara, Yasushi Iwata, Hiroyuki Ishii, Akira Kano, Yusei Kusaka, Kyosuke Ito, Tomoo Murata
  • Publication number: 20230070997
    Abstract: A metal removal agent used when removing Mg from an aluminum alloy melt whose raw material is scrap or the like and used for formation of a molten salt layer that takes in Mg from an aluminum alloy melt. The metal removal agent contains: a specific metal element one or more of Cu, Zn, or Mn; a specific halogen element one or more of Cl or Br; and Mg. The metal removal agent may also contain: a base halide that serves as a base material of the molten salt layer; and a specific metal halide that is a compound of a specific metal element and a specific halogen element. When the molten salt layer formed using the agent and the aluminum alloy melt containing Mg are brought into contact with each other, Mg is taken into the molten salt layer side from the aluminum alloy melt side and efficiently removed.
    Type: Application
    Filed: January 11, 2021
    Publication date: March 9, 2023
    Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA TSUSHO CORPORATION
    Inventors: Jun YAOKAWA, Takuma MINOURA, Kazuma HIBI, Hiroshi KAWAHARA, Yasushi IWATA, Hiroyuki ISHII, Akira KANO, Yusei KUSAKA, Kyosuke ITO, Tomoo MURATA
  • Publication number: 20230043661
    Abstract: A method with which Mg can be removed from aluminum alloy melt whose raw material is scrap or the like. Metal removal method includes processing step of forming molten salt layer in contact with aluminum alloy melt containing Mg which covers at least part of the surface of the aluminum alloy melt. This method allows Mg to be taken in from aluminum alloy melt to molten salt layer and removed. Molten salt layer contains specific halogen element that is one or more of Cl or Br and specific metal element that is one or more of Cu, Zn, or Mn. The specific metal element is supplied as an oxide of the specific metal element to the molten salt layer. At that time, the molten salt layer contains Mg. The step of removing Mg is performed by disposing a conductor that bridges the aluminum alloy melt and the molten salt layer.
    Type: Application
    Filed: January 11, 2021
    Publication date: February 9, 2023
    Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA TSUSHO CORPORATION
    Inventors: Takuma MINOURA, Jun YAOKAWA, Kazuma HIBI, Hiroshi KAWAHARA, Yasushi IWATA, Hiroyuki ISHII, Akira KANO, Yusei KUSAKA, Kyosuke ITO, Tomoo MURATA
  • Publication number: 20220106666
    Abstract: A recycling method for aluminum alloy is capable of offering a recycled Al alloy (melt), in which the Fe concentration is efficiently reduced, while using Al alloy scrap and the like as raw materials. The method includes: a preparation step of preparing a first melt by melting an Fe.Mn-containing material that contains Fe and Mn and an Al alloy raw material; a crystallization step of holding the first melt at a separation temperature at which an Fe compound crystallizes; and an extraction step of extracting a second melt obtained by removing at least part of the Fe compound crystallized from the first melt. The Fe.Mn-containing material preferably has a mass ratio of Mn to Fe (Mn/Fe) of, for example, 2 or more.
    Type: Application
    Filed: November 25, 2019
    Publication date: April 7, 2022
    Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA, TOYOTA TSUSHO CORPORATION
    Inventors: Takuma MINOURA, Jun YAOKAWA, Yasushi IWATA, Hiroshi KAWAHARA, Kazuma HIBI, Noriyuki UENO, Akira KANO, Yusei KUSAKA, Kyosuke ITO, Tomoo MURATA
  • Patent number: 8421512
    Abstract: A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: April 16, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Tomoo Murata, Takeo Yamashita
  • Publication number: 20110316603
    Abstract: A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 29, 2011
    Inventors: Tomoo MURATA, Takeo YAMASHITA
  • Patent number: 7962047
    Abstract: When an optical signal that is a wide dynamic range and different in level depending on burst signals is input as in a GPON system, a preamplifier can stably control the gain within a short preamble. The gain changeover of the preamplifier is controlled by the aid of timing information that is extracted from a data signal as data count number, to change over the gain at a high speed and with high precision. A level detector, a preamble recovery, a counter, and a control circuit are disposed within the preamplifier in addition to a TIA main body. In order to suppress the band deterioration or the phase margin reduction which are attributable to the gain changeover, there is provided a bias terminal for conducting a current injection and a current drawing with respect to the signal amplification transistor of the TIA main body.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: June 14, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Tomoo Murata
  • Patent number: 7903013
    Abstract: Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: March 8, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kenichiro Yamaguchi, Atsushi Okumura, Mitsugu Kusunoki, Tomoo Murata
  • Publication number: 20100110751
    Abstract: In a configuration having a nonvolatile memory and a volatile memory, when storage information of the nonvolatile memory is changed and an abnormal operation occurs due to temporary blackout, ?-ray or others, the abnormal operation is recovered to a normal operation regardless of the presence of the detection of the abnormal operation. A reset to be inputted to the nonvolatile memory is collectively transmitted for each 1 bit, each 1 word or each predetermined arbitrary bit, and the collectively transmitted reset serving as one unit is periodically transmitted, so that the abnormal operation is recovered to a normal operation without input signals from outside even if the storage information of the nonvolatile memory is changed due to temporary blackout, ?-ray or others.
    Type: Application
    Filed: October 22, 2009
    Publication date: May 6, 2010
    Inventors: Kentaro Miyajima, Takeo Yamashita, Tomoo Murata
  • Publication number: 20100072821
    Abstract: Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.
    Type: Application
    Filed: July 22, 2009
    Publication date: March 25, 2010
    Inventors: Kenichiro YAMAGUCHI, Atsushi Okumura, Mitsugu Kusunoki, Tomoo Murata
  • Publication number: 20080205906
    Abstract: When an optical signal that is a wide dynamic range and different in level depending on burst signals is input as in a GPON system, a preamplifier can stably control the gain within a short preamble. The gain changeover of the preamplifier is controlled by the aid of timing information that is extracted from a data signal as data count number, to change over the gain at a high speed and with high precision. A level detector, a preamble recovery, a counter, and a control circuit are disposed within the preamplifier in addition to a TIA main body. In order to suppress the band deterioration or the phase margin reduction which are attributable to the gain changeover, there is provided a bias terminal for conducting a current injection and a current drawing with respect to the signal amplification transistor of the TIA main body.
    Type: Application
    Filed: December 19, 2007
    Publication date: August 28, 2008
    Inventor: Tomoo Murata
  • Patent number: 7245019
    Abstract: In a method of manufacturing a semiconductor device having a first wiring extending in a first direction and a second wiring connected to the first wiring through a connection and extending in a second direction orthogonal to the first direction, the second wiring having a surplus portion projecting from the connection in a direction opposite to the second direction, the first and second wirings are arranged such that a center of the connection is offset in the second direction from a center of the first wiring, and a projecting portion of the first wiring is disposed under the connection.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: July 17, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tomoo Murata, Shinobu Yabuki, Takeo Yamashita
  • Publication number: 20040056280
    Abstract: In a method of manufacturing a semiconductor device comprising: having a first wiring extending in a first direction; and a second wiring connected to the first wiring through a connection and extending in a second direction orthogonal to the first direction, the second wiring having a surplus portion projecting from the connection in a direction opposite to the second direction, the first and second wirings are arranged such that a center of the connection is offset in the second direction from a center of the first wiring, and a projecting portion of the first wiring is disposed under the connection.
    Type: Application
    Filed: August 26, 2003
    Publication date: March 25, 2004
    Inventors: Tomoo Murata, Shinobu Yabuki, Takeo Yamashita