Patents by Inventor Tomoo Nakayama

Tomoo Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387219
    Abstract: A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.
    Type: Application
    Filed: March 16, 2023
    Publication date: November 30, 2023
    Inventors: Futoshi KOMATSU, Tomoo NAKAYAMA, Katsuhiro UCHIMURA, Hiroshi INAGAWA
  • Patent number: 11262500
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 1, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba, Seigo Namioka, Tomoo Nakayama
  • Publication number: 20210184054
    Abstract: A gallium oxide diode includes: a gallium oxide substrate having an n-type gallium oxide drift layer; an anode electrode of a metal film formed over a front surface of the n-type gallium oxide drift layer; a cathode electrode formed over a rear surface of the gallium oxide substrate; and a reaction layer of a metal oxide film of p-type conductivity formed between the anode electrode and the n-type gallium oxide drift layer. Further, a manufacturing method of a gallium oxide diode includes steps of forming an anode electrode of a metal film over an n-type gallium oxide drift layer formed over a gallium oxide substrate; and forming a reaction layer between the anode electrode and the n-type gallium oxide drift layer by performing a heat treatment to the gallium oxide substrate after forming the anode electrode, the reaction layer being made of a metal oxide film with p-type conductivity.
    Type: Application
    Filed: November 18, 2020
    Publication date: June 17, 2021
    Inventors: Hironobu MIYAMOTO, Masami SAWADA, Tatsuya USAMI, Tomoo NAKAYAMA
  • Publication number: 20210165160
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA, Seigo NAMIOKA, Tomoo NAKAYAMA
  • Patent number: 10818813
    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoo Nakayama, Shinichi Watanuki, Futoshi Komatsu, Teruhiro Kuwajima, Takashi Ogura, Hiroyuki Okuaki, Shigeaki Shimizu
  • Patent number: 10714330
    Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 14, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoo Nakayama, Tatsuya Usami
  • Patent number: 10553734
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
  • Patent number: 10355161
    Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
  • Publication number: 20190198703
    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.
    Type: Application
    Filed: November 13, 2018
    Publication date: June 27, 2019
    Inventors: Tomoo NAKAYAMA, Shinichi WATANUKI, Futoshi KOMATSU, Teruhiro KUWAJIMA, Takashi OGURA, Hiroyuki OKUAKI, Shigeaki SHIMIZU
  • Patent number: 10211352
    Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama, Takashi Ogura, Teruhiro Kuwajima
  • Publication number: 20190006535
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film.
    Type: Application
    Filed: May 15, 2018
    Publication date: January 3, 2019
    Inventors: Teruhiro KUWAJIMA, Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA
  • Publication number: 20180366321
    Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.
    Type: Application
    Filed: March 23, 2018
    Publication date: December 20, 2018
    Inventors: Tomoo NAKAYAMA, Tatsuya USAMI
  • Patent number: 10121927
    Abstract: A provided semiconductor device includes a Ge photodiode having proper diode characteristics. A groove is provided on a germanium growth protective film, a p-type silicon layer, and a first insulating film from the top surface of the germanium growth protective film without reaching the major surface of a semiconductor substrate. An i-type germanium layer and an n-type germanium layer are embedded in the groove with a seed layer interposed between the layers and the groove, the seed layer being made of amorphous silicon, polysilicon, or silicon germanium. The i-type germanium layer and the n-type germanium layer do not protrude from the top surface of the germanium growth protective film, thereby forming a flat second insulating film having a substantially even thickness on the n-type germanium layer and the germanium growth protective film.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Tomoo Nakayama
  • Patent number: 10084078
    Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: September 25, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoo Nakayama, Hiroshi Kawaguchi
  • Publication number: 20180138325
    Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 17, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA, Takashi OGURA, Teruhiro KUWAJIMA
  • Publication number: 20180090636
    Abstract: A provided semiconductor device includes a Ge photodiode having proper diode characteristics. A groove is provided on a germanium growth protective film, a p-type silicon layer, and a first insulating film from the top surface of the germanium growth protective film without reaching the major surface of a semiconductor substrate. An i-type germanium layer and an n-type germanium layer are embedded in the groove with a seed layer interposed between the layers and the groove, the seed layer being made of amorphous silicon, polysilicon, or silicon germanium. The i-type germanium layer and the n-type germanium layer do not protrude from the top surface of the germanium growth protective film, thereby forming a flat second insulating film having a substantially even thickness on the n-type germanium layer and the germanium growth protective film.
    Type: Application
    Filed: July 21, 2017
    Publication date: March 29, 2018
    Inventor: Tomoo NAKAYAMA
  • Publication number: 20180083154
    Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 22, 2018
    Inventors: Teruhiro KUWAJIMA, Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA
  • Publication number: 20170170306
    Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.
    Type: Application
    Filed: November 25, 2016
    Publication date: June 15, 2017
    Inventors: Tomoo NAKAYAMA, Hiroshi KAWAGUCHI
  • Patent number: 9589954
    Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Mitsuiki, Tomoo Nakayama, Shigeaki Shimizu, Hiroyuki Okuaki
  • Publication number: 20160056233
    Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.
    Type: Application
    Filed: August 5, 2015
    Publication date: February 25, 2016
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira MITSUIKI, Tomoo NAKAYAMA, Shigeaki SHIMIZU, Hiroyuki OKUAKI