Patents by Inventor Tomoo Yamasaki
Tomoo Yamasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11462501Abstract: An interconnect substrate includes an insulating layer and an interconnect layer formed on a surface of the insulating layer, wherein the surface of the insulating layer has grooves formed therein, the grooves having a meander shape on an order of nanometers in a plan view, and wherein the interconnect layer has anchor portions fitted into the grooves.Type: GrantFiled: October 21, 2020Date of Patent: October 4, 2022Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Ryo Fukasawa, Tomoo Yamasaki
-
Publication number: 20210125953Abstract: An interconnect substrate includes an insulating layer and an interconnect layer formed on a surface of the insulating layer, wherein the surface of the insulating layer has grooves formed therein, the grooves having a meander shape on an order of nanometers in a plan view, and wherein the interconnect layer has anchor portions fitted into the grooves.Type: ApplicationFiled: October 21, 2020Publication date: April 29, 2021Inventors: Ryo FUKASAWA, Tomoo YAMASAKI
-
Patent number: 10261110Abstract: A probe guide plate includes: a silicon substrate including one surface and the other surface opposite to the one surface; a through hole formed through the silicon substrate to extend from the one surface of the silicon substrate to the other surface of the silicon substrate; a silicon oxide layer formed on the one surface of the silicon substrate, the other surface of the silicon substrate, and an inner wall surface of the through hole; and a protective insulating layer formed on the silicon oxide layer. The protective insulating layer is formed on at least one of the one surface and the other surface of the silicon substrate via the silicon oxide layer, and partially formed on the inner wall surface of the through hole via the silicon oxide layer.Type: GrantFiled: November 21, 2016Date of Patent: April 16, 2019Assignees: SHINKO ELECTRIC INDUSTRIES CO., LTD., JAPAN ELECTRONIC MATERIALS CORPORATIONInventors: Yuichiro Shimizu, Kosuke Fujihara, Tomoo Yamasaki, Chikaomi Mori
-
Patent number: 9780032Abstract: A wiring substrate includes a first insulation layer, a wiring layer formed on an upper surface of the first insulation layer, a barrier film that covers the upper surface of the first insulation layer, an upper surface of the wiring layer, and side surfaces of the wiring layer, and a second insulation layer that covers an upper surface of the barrier film and side surfaces of the barrier film. The barrier film is an alumina film containing carbon atoms, and the alumina film has a carbon atom content rate that is in the range of 0.2 atomic % to 3.6 atomic %.Type: GrantFiled: December 16, 2016Date of Patent: October 3, 2017Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tomoo Yamasaki, Kazuhiro Fujita
-
Publication number: 20170186684Abstract: A wiring substrate includes a first insulation layer, a wiring layer formed on an upper surface of the first insulation layer, a barrier film that covers the upper surface of the first insulation layer, an upper surface of the wiring layer, and side surfaces of the wiring layer, and a second insulation layer that covers an upper surface of the barrier film and side surfaces of the barrier film. The barrier film is an alumina film containing carbon atoms, and the alumina film has a carbon atom content rate that is in the range of 0.2 atomic % to 3.6 atomic %.Type: ApplicationFiled: December 16, 2016Publication date: June 29, 2017Inventors: TOMOO YAMASAKI, KAZUHIRO FUJITA
-
Publication number: 20170146569Abstract: A probe guide plate includes: a silicon substrate including one surface and the other surface opposite to the one surface; a through hole formed through the silicon substrate to extend from the one surface of the silicon substrate to the other surface of the silicon substrate; a silicon oxide layer formed on the one surface of the silicon substrate, the other surface of the silicon substrate, and an inner wall surface of the through hole; and a protective insulating layer formed on the silicon oxide layer. The protective insulating layer is formed on at least one of the one surface and the other surface of the silicon substrate via the silicon oxide layer, and partially formed on the inner wall surface of the through hole via the silicon oxide layer.Type: ApplicationFiled: November 21, 2016Publication date: May 25, 2017Inventors: Yuichiro Shimizu, Kosuke Fujihara, Tomoo Yamasaki, Chikaomi Mori
-
Patent number: 9006586Abstract: One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.Type: GrantFiled: June 21, 2012Date of Patent: April 14, 2015Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki
-
Patent number: 8878077Abstract: A method of manufacturing a wiring substrate, includes forming a laminated body in which a nickel copper alloy layer is formed via an insulating resin layer, on a first wiring layer, forming a via hole reaching the first wiring layer in the nickel copper alloy layer and the insulating resin layer, applying a desmear process to an inside of the via hole, forming a seed layer on the nickel copper alloy layer and an inner surface of the via hole, forming a plating resist in which an opening portion is provided on a part containing the via hole, forming a metal plating layer in the opening portion in the plating resist by an electroplating, removing the plating resist, and forming a second wiring layer by etching the seed layer and the nickel copper alloy layer while using the metal plating layer as a mask.Type: GrantFiled: October 24, 2011Date of Patent: November 4, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takashi Ito, Tomoo Yamasaki, Yuta Sakaguchi
-
Patent number: 8729401Abstract: A wiring substrate includes a composite substrate including an oxidized aluminum substrate portion in which a large number of penetration conductors penetrating in a thickness direction are provided, and a frame-like aluminum substrate portion provided around the oxidized aluminum substrate portion, and a wiring layer of n layers (n is an integer of 1 or more) connected to the penetration conductors.Type: GrantFiled: February 22, 2011Date of Patent: May 20, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tomoo Yamasaki, Michio Horiuchi
-
Patent number: 8638542Abstract: A capacitor includes a dielectric substrate and a large number of filamentous conductors formed to penetrate through the dielectric substrate in a thickness direction thereof. An electrode is connected to only respective one ends of a plurality of filamentous conductors constituting one of groups each composed of a plurality of filamentous conductors. The electrode is disposed in at least one position on each of both surfaces of the dielectric substrate, or in at least two positions on one of the surfaces. Further, an insulating layer is formed on each of both surfaces of the dielectric substrate so as to cover regions between the electrodes, and a conductor layer is formed on the corresponding insulating layer integrally with a desired number of electrodes.Type: GrantFiled: July 9, 2010Date of Patent: January 28, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Yukio Shimizu, Tomoo Yamasaki, Yuta Sakaguchi
-
Publication number: 20120327626Abstract: One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.Type: ApplicationFiled: June 21, 2012Publication date: December 27, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki
-
Patent number: 8288659Abstract: A wiring board includes a substrate having a surface made of an insulating resin. An adhesion layer is formed on the substrate. A wiring layer is formed on the adhesion layer. The adhesion layer is formed by a nitrided NiCu alloy containing nitrogen therein. A nitrogen content of the nitrided NiCu alloy is within a range from 1 atoms % to 5 atoms %.Type: GrantFiled: August 27, 2010Date of Patent: October 16, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventor: Tomoo Yamasaki
-
Patent number: 8242612Abstract: A wiring board includes a core substrate including an insulation base member; linear conductors configured to pierce from a first surface of the insulation base member to a second surface of the insulation base member; a ground wiring group including a first ground wiring formed on the first surface of the core substrate, and a belt-shaped second ground wiring formed on the second surface of the core substrate and electrically connected to the first ground wiring by way of a part of the linear conductors; and an electric power supply wiring group including a first electric power supply wiring formed on the first surface, and a second electric power supply wiring formed on the second surface and electrically connected to the first electric power supply wiring by way of a part of the plural linear conductors.Type: GrantFiled: June 11, 2010Date of Patent: August 14, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki, Yuta Sakaguchi
-
Publication number: 20120103667Abstract: A method of manufacturing a wiring substrate, includes forming a laminated body in which a nickel copper alloy layer is formed via an insulating resin layer, on a first wiring layer, forming a via hole reaching the first wiring layer in the nickel copper alloy layer and the insulating resin layer, applying a desmear process to an inside of the via hole, forming a seed layer on the nickel copper alloy layer and an inner surface of the via hole, forming a plating resist in which an opening portion is provided on a part containing the via hole, forming a metal plating layer in the opening portion in the plating resist by an electroplating, removing the plating resist, and forming a second wiring layer by etching the seed layer and the nickel copper alloy layer while using the metal plating layer as a mask.Type: ApplicationFiled: October 24, 2011Publication date: May 3, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Takashi ITO, Tomoo YAMASAKI, Yuta SAKAGUCHI
-
Patent number: 8138609Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.Type: GrantFiled: July 8, 2010Date of Patent: March 20, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki, Yuta Sakaguchi
-
Patent number: 8066862Abstract: A manufacturing method of a wiring board includes a sticking layer forming step; a resist film forming step of forming a resist film on an upper surface of the sticking layer, the resist film having an opening exposing the upper surface of the sticking layer; a metal layer forming step of forming a metal layer, so as to cover an upper surface of the resist film and cover a side surface of the resist film and the upper surface of the sticking layer forming the opening for forming the wiring; a plating film forming step of filling with a plating film the opening for forming the wiring; a metal layer and plating film removing step; a resist film removing step; and a sticking layer removing step of removing the sticking layer of an unnecessary part not covered with the metal layer, after the resist film removing step.Type: GrantFiled: November 28, 2008Date of Patent: November 29, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tomoo Yamasaki, Katsuya Fukase
-
Publication number: 20110220404Abstract: A wiring substrate includes a composite substrate including an oxidized aluminum substrate portion in which a large number of penetration conductors penetrating in a thickness direction are provided, and a frame-like aluminum substrate portion provided around the oxidized aluminum substrate portion, and a wiring layer of n layers (n is an integer of 1 or more) connected to the penetration conductors.Type: ApplicationFiled: February 22, 2011Publication date: September 15, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Tomoo Yamasaki, Michio Horiuchi
-
Publication number: 20110061916Abstract: A wiring board includes a substrate having a surface made of an insulating resin. An adhesion layer is formed on the substrate. A wiring layer is formed on the adhesion layer. The adhesion layer is formed by a nitrided NiCu alloy containing nitrogen therein. A nitrogen content of the nitrided NiCu alloy is within a range from 1 atoms % to 5 atoms %.Type: ApplicationFiled: August 27, 2010Publication date: March 17, 2011Inventor: Tomoo Yamasaki
-
Publication number: 20110018144Abstract: A wiring board includes a core substrate including an insulation base member; linear conductors configured to pierce from a first surface of the insulation base member to a second surface of the insulation base member; a ground wiring group including a first ground wiring formed on the first surface of the core substrate, and a belt-shaped second ground wiring formed on the second surface of the core substrate and electrically connected to the first ground wiring by way of a part of the linear conductors; and an electric power supply wiring group including a first electric power supply wiring formed on the first surface, and a second electric power supply wiring formed on the second surface and electrically connected to the first electric power supply wiring by way of a part of the plural linear conductors.Type: ApplicationFiled: June 11, 2010Publication date: January 27, 2011Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki, Yuta Sakaguchi
-
Publication number: 20110013340Abstract: A capacitor includes a dielectric substrate and a large number of filamentous conductors formed to penetrate through the dielectric substrate in a thickness direction thereof. An electrode is connected to only respective one ends of a plurality of filamentous conductors constituting one of groups each composed of a plurality of filamentous conductors. The electrode is disposed in at least one position on each of both surfaces of the dielectric substrate, or in at least two positions on one of the surfaces. Further, an insulating layer is formed on each of both surfaces of the dielectric substrate so as to cover regions between the electrodes, and a conductor layer is formed on the corresponding insulating layer integrally with a desired number of electrodes.Type: ApplicationFiled: July 9, 2010Publication date: January 20, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTDInventors: Michio HORIUCHI, Yasue Tokutake, Yuichi Matsuda, Yukio Shimizu, Tomoo Yamasaki, Yuta Sakaguchi