Abstract: The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.

Abstract: The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.

Abstract: A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on t

Abstract: Particular blocks are a boot block and parameter block having a storage capacity smaller than that of a general block. In the case where a boot block is not required, a signal BOOTE is set at an L level. In the case where a signal BLKSEL is at an H level in an erasure mode, a control unit selects four blocks aligned in a horizontal direction at the same time. The control unit also selects two blocks simultaneously in the vertical direction. As a result, the particular eight blocks are selected. The boot block and parameter block can be erased collectively as one block having a capacity similar to that of a general block. Therefore, a flash memory corresponding to the case of including a boot block and not including a boot block can be implemented simultaneously with one chip. Thus, the designing and fabrication process can be simplified.

Abstract: A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on t

Abstract: A non-volatile semiconductor memory device includes a bank pointer, in which a signal for designating an operating mode to be performed is generated according to coincidence/non-coincidence of prescribed bits of address signals supplied from an address buffer, and the generated signal is supplied to an internal control circuit. Thus, necessary data can be read out from the non-volatile semiconductor memory device at high speed, so that usability of the device is improved.

Abstract: An external read sense amplifier for reading out a data to an outside and an internal verify sense amplifier for reading out a data for an internal operation are provided, separately from each other, to a plurality of banks. Preferably, an internal verify sense amplifier is provided for each prescribed number of memory blocks. There is provided a nonvolatile semiconductor memory device with a background operation function, having a reduced chip occupancy area.

Abstract: A memory transistor for a lock bit, holding information on whether a memory block can be erased/reprogrammed, is provided in the same column as that of a plurality of dummy cells. Since a sub bit line for reading the lock bit is electrically isolated from a sub bit line for dummy cell, accurate lock-bit reading is possible even when the dummy cell is over erased. Thus, a nonvolatile semiconductor memory device advantageous in reliability and operation time can be provided.

Abstract: An external read sense amplifier for reading out a data to an outside and an internal verify sense amplifier for reading out a data for an internal operation are provided, separately from each other, to a plurality of banks. Preferably, an internal verify sense amplifier is provided for each prescribed number of memory blocks. There is provided a nonvolatile semiconductor memory device with a background operation function, having a reduced chip occupancy area.

Abstract: A non-volatile semiconductor memory device includes a bank pointer, in which a signal for designating an operating mode to be performed is generated according to coincidence/non-coincidence of prescribed bits of address signals supplied from an address buffer, and the generated signal is supplied to an internal control circuit. Thus, necessary data can be read out from the non-volatile semiconductor memory device at high speed, so that usability of the device is improved.

Abstract: A memory cell array is divided into a plurality of memory cell blocks each collectively subjected to an erasing operation as a unit. A P well regions for memory cell transistors and an N well region for electrically separating the P well regions are provided. Select transistors are formed in the same P well region as the memory cell transistor connected to the corresponding sub bit line of P well regions.

Abstract: In response to complementary clock signals provided from a driver, a charge pump operates to provide an output voltage which is a down-converted negative voltage. The voltage between this output voltage and a predetermined positive reference voltage is capacitance-divided by capacitors. The capacitance-divided positive voltage is applied to a comparator, whereby a reference voltage is compared with the above positive voltage. An output signal of the comparator is applied to the driver. In response, the driver controls the operation of the charge pump, whereby the output voltage is clamped at a predetermined voltage level for output.

Abstract: An internal potential generation circuit operates with the potential levels of an output node N.sub.H1 of a first boosting circuit and an output node N.sub.H2 of a second boosting circuit maintained in common in response to a high voltage switch circuit attaining a conductive state at the initial stage of the operation of the internal potential generation circuit. After the output potential level of the second boosting circuit arrives at a predetermined potential level, the high voltage switch circuit is cut off, whereby the first and second boosting circuits drive independently the potential level of corresponding output nodes.

Abstract: In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

Abstract: In a flash memory, a reading bit line and a writing bit line are provided corresponding to a respective column of memory cells. A well voltage and a voltage on a source line can be controlled for each sub-block. Accordingly, data can be read at a sub-block while data can be written/erased at another sub-block, and therefore, the capacity ratio of a back ground operation region to the main memory region can be changed as desired.

Abstract: In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

Abstract: In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

Abstract: A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

Abstract: A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

Abstract: A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.