Patents by Inventor Tomosuke Yoshida

Tomosuke Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10460983
    Abstract: A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 29, 2019
    Assignee: SHIN-ETSU HANDOTAI CO.,LTD.
    Inventors: Taishi Wakabayashi, Kenji Meguro, Masatake Nakano, Shinichiro Yagi, Tomosuke Yoshida
  • Publication number: 20170040210
    Abstract: A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.
    Type: Application
    Filed: March 4, 2015
    Publication date: February 9, 2017
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Taishi WAKABAYASHI, Kenji MEGURO, Masatake NAKANO, Shinichiro YAGI, Tomosuke YOSHIDA
  • Publication number: 20150011079
    Abstract: The present invention provides a method for manufacturing a silicon epitaxial wafer, characterized in that a silicon epitaxial layer is formed on an N-type silicon single crystal wafer manufactured by doping with arsenic to set a resistivity to 1.0 to 1.7 m?cm and further doping with carbon, nitrogen, or both carbon and nitrogen. As a result, there can be provided the method for manufacturing a silicon epitaxial wafer that can suppress occurrence of stacking faults at the time of performing epitaxial growth on the arsenic-doped super-low resistance silicon single crystal wafer.
    Type: Application
    Filed: January 21, 2013
    Publication date: January 8, 2015
    Inventors: Tomosuke Yoshida, Hisashi Kashino
  • Patent number: 8697547
    Abstract: A method for manufacturing a silicon epitaxial wafer, including vapor-phase growing a silicon single crystal thin film on a silicon single crystal substrate in a hydrogen atmosphere while supplying a source gas; and cooling a silicon epitaxial wafer having the formed silicon single crystal thin film by calculating a temperature at which a standard value or a process average value of concentration of an evaluation target impurity present in the silicon single crystal thin film coincides with solubility limit concentration of the evaluation target impurity and setting a cooling rate of the silicon epitaxial wafer after the film formation to be less than 20° C./sec in a temperature range of at least plus or minus 50° C. from the calculated temperature.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: April 15, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Tomosuke Yoshida
  • Publication number: 20120231612
    Abstract: A method for manufacturing a silicon epitaxial wafer, including vapor-phase growing a silicon single crystal thin film on a silicon single crystal substrate in a hydrogen atmosphere while supplying a source gas; and cooling a silicon epitaxial wafer having the formed silicon single crystal thin film by calculating a temperature at which a standard value or a process average value of concentration of an evaluation target impurity present in the silicon single crystal thin film coincides with solubility limit concentration of the evaluation target impurity and setting a cooling rate of the silicon epitaxial wafer after the film formation to be less than 20° C./sec in a temperature range of at least plus or minus 50° C. from the calculated temperature.
    Type: Application
    Filed: November 11, 2010
    Publication date: September 13, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Tomosuke Yoshida
  • Patent number: 7713851
    Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: May 11, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Publication number: 20090038540
    Abstract: In a vapor phase growth apparatus, epitaxial growth is performed with respect to a wafer having a CVD film formed on a back surface thereof as a wafer for monitoring that is used to guarantee a resistance and/or measure a thickness of an epitaxial layer, then epitaxial growth is performed with respect to a wafer as a dummy or a vapor phase growth apparatus is activated under conditions for performing epitaxial growth without using a wafer, and subsequently epitaxial growth is carried out with respect to a wafer as a product, thereby manufacturing an epitaxial wafer. As a result, when using a wafer having no CVD film to manufacture an epitaxial wafer that is used to fabricate an imaging device, e.g., a CCD or a CMOS image sensor, a method capable of effectively avoiding heavy-metal contamination and manufacturing a high-quality epitaxial layer is provided.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 12, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tomosuke Yoshida, Naohisa Toda
  • Publication number: 20070269338
    Abstract: A silicon epitaxial wafer 100 is formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by means of a CZ method, and doped with boron so that a resistivity thereof is less than 0.018 ?·cm. The silicon single crystal substrate 1 has a density of bulk stacking faults 13 in the silicon single crystal substrate 1 in the range of 1×108 cm?3 or higher and 3×109 cm?3 or lower. Thereby, provided is a silicon epitaxial wafer having a boron doped p+ CZ substrate with a resistivity of 0.018?·cm or lower, and a state of formation of oxygen precipitates can be adjusted adequately so as to secure a sufficient IG effect and to suppress a problem of bow and deformation of a substrate, despite that sizes of oxygen precipitates is so small to be observed accurately.
    Type: Application
    Filed: June 27, 2005
    Publication date: November 22, 2007
    Applicant: Shin-Etsu Handotai Co., Ltd
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Publication number: 20070243699
    Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
    Type: Application
    Filed: August 3, 2005
    Publication date: October 18, 2007
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Patent number: 7270708
    Abstract: A susceptor (10) supporting a semiconductor substrate (W) in a vapor phase growth, wherein a pocket (11) is formed on an upper surface of the susceptor to arrange the semiconductor substrate (W) inside thereof. The pocket (11) has a two-stage structure having an upper stage pocket (11a) for supporting an outer peripheral edge portion of the semiconductor substrate (W) and a lower stage pocket (11b) formed on a lower stage of a center side from the upper stage pocket (11a). A hole (12) penetrated to a rear surface of the susceptor and opened in the vapor phase growth is formed in the lower stage pocket (11b).
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 18, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tomosuke Yoshida, Takeshi Arai, Kenji Akiyama, Hiroki Ose
  • Publication number: 20060281283
    Abstract: A silicon epitaxial wafer (W) comprising: a silicon single crystal substrate (1) having a COP (100) on a main surface (11), and a silicon epitaxial layer (2) grown by vapor phase epitaxy on the main surface (11) of the silicon single crystal substrate (1), wherein the main surface (11) is inclined from a (100) plane in a [011] direction or a [0-1-1] direction by an angle ? with respect to a [100] axis as well as inclined from a (100) plane in a [01-1] direction or a [0-11] direction by an angle ? with respect to a [100] axis, and at least one of the angle ? and the angle ? is from 0° to 15?.
    Type: Application
    Filed: April 2, 2004
    Publication date: December 14, 2006
    Applicant: Shin-Etsu Handotai Co., LTD.
    Inventors: Tomosuke Yoshida, Hitoshi Tsunoda, Masahiro Kato
  • Publication number: 20040255843
    Abstract: A susceptor (10) supporting a semiconductor substrate (W) in a vapor phase growth, wherein a pocket (11) is formed on an upper surface of the susceptor to arrange the semiconductor substrate (W) inside thereof. The pocket (11) has a two-stage structure having an upper stage pocket (11a) for supporting an outer peripheral edge portion of the semiconductor substrate (W) and a lower stage pocket (11b) formed on a lower stage of a center side from the upper stage pocket (11a). A hole (12) penetrated to a rear surface of the susceptor and opened in the vapor phase growth is formed in the lower stage pocket (11b).
    Type: Application
    Filed: April 20, 2004
    Publication date: December 23, 2004
    Inventors: Tomosuke Yoshida, Takeshi Arai, Kenji Akiyama, Hiroki Ose
  • Patent number: 6599603
    Abstract: The present invention provides a CZ silicon wafer, wherein the wafer includes rod-like void defects and/or plate-like void defects inside thereof, and a CZ silicon wafer, wherein the silicon wafer includes void defects inside the wafer, a maximum value of a ratio between long side length L1 and short side length L2 (L1/L2) in an optional rectangle circumscribed the void defect image projected on an optional {110} plane is 2.5 or more, and the silicon wafer including rod-like void defects and/or plate-like void defects inside the wafer, wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 &mgr;m after the heat treatment is ½ or less than that of inside the wafer. According to this, the silicon wafer, which is suitable for expanding reducing effect of void defects by heat treatment up to a deeper region, can be obtained.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: July 29, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Kato, Masaro Tamatsuka, Osamu Imai, Akihiro Kimura, Tomosuke Yoshida
  • Patent number: 6162708
    Abstract: There is disclosed a method for producing an epitaxial silicon single crystal wafer comprising the steps of growing a silicon single crystal ingot wherein nitrogen is doped by Czochralski method, slicing the silicon single crystal ingot to provide a silicon single crystal wafer, and forming an epitaxial layer in the surface layer portion of the silicon single crystal wafer. There can be manufactured easily and in high productivity an epitaxial silicon monocrystal wafer which has high gettering capability when a substrate having a low boron concentration is used, a low concentration of heavy metal impurity, and an excellent crystallinity.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: December 19, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masaro Tamatsuka, Ken Aihara, Tomosuke Yoshida
  • Patent number: 5841532
    Abstract: A method and apparatus for evaluating an oxygen concentration in a semiconductor silicon single crystal highly doped with boron at a low cost with a high sensitivity and high reproducibility. The single crystal, which is doped with boron of a high concentration of 10.sup.17 atoms/cm.sup.3 or higher, is irradiated with a light having a greater energy than that of bandgap of the semiconductor silicon while holding the single crystal at a temperature of room temperature to 50 K and photoluminescence intensities in the vicinity of a photon energy of 0.96 eV of a photoluminescence spectrum emitted from the single crystal under the above irradiation are measured to evaluate an oxygen concentration in the single crystal.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: November 24, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tomosuke Yoshida, Yutaka Kitagawara