Patents by Inventor Tomotoshi Inoue

Tomotoshi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming wirings for integrated circuits by electroplating
    Patent number: 5556814
    Abstract: A method for forming wirings of an integrated circuit comprises a step of forming wirings on a substrate, a step of coating the wirings with a thin under metal layer, a step of coating the under metal layer with a mask except a part of the under metal layer, a first etching step of removing the under metal layer which is not coated by the mask to expose upper portions of at least ones of the wirings, an electroplating step of depositing a plating metal layer on the exposed upper portions, a step of removing the mask, and a second etching step of removing all of the remaining under metal layer, whereby said plating metal layer is formed by substantially same material as that of the exposed upper portions or by a material which can be closely contacted with the exposed upper portions and whereby said under metal layer is formed by a material which can be preferentially removed from the exposed upper portions.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: September 17, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomotoshi Inoue, Misao Yoshimura
  • Metal semiconductor device and method for producing the same
    Patent number: 5273937
    Abstract: A metal semiconductor device, in which an electrode is formed on a semiconductor substrate to form a Schottky junction therebetween, and the electrode has an oxide film having a first thickness on its upper surface and a non-oxidized portion having a second thickness from the Schottky junction. A method for producing the metal semiconductor device is also disclosed, in which a conductor layer formed on the semiconductor substrate is oxidized in a gas containing oxygen, and a capless annealing of the semiconductor substrate having the oxidized conductor layer thereon is conducted in an atmosphere containing arsenic.
    Type: Grant
    Filed: October 15, 1991
    Date of Patent: December 28, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nishihori, Tomotoshi Inoue, Kenichi Tomita, Hitoshi Mikami, Masami Nagaoka, Naotaka Uchitomi
  • Semiconductor device having an improved air-bridge lead structure
    Patent number: 5148260
    Abstract: A semiconductor device having an improved air-bridge lead structure is provided. The improved air-bridge lead structure has a higher mechanical strength and a lower electric resistance with a smaller electric capacitance.
    Type: Grant
    Filed: September 7, 1990
    Date of Patent: September 15, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomotoshi Inoue, Toshiyuki Terada, Kenichi Tomita
  • Semiconductor integrated circuit device having a hollow multi-layered lead structure
    Patent number: 5034799
    Abstract: A highly reliable semiconductor integrated circuit device having a hollow multi-layered lead structure is provided. The device comprises lead-supporting columns that can securely support the multi-layered leads and can also efficiently radiate heat generated in operation.
    Type: Grant
    Filed: February 14, 1990
    Date of Patent: July 23, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Tomita, Tomotoshi Inoue, Toshiyuki Terada