Patents by Inventor Tomotoshi Satoh
Tomotoshi Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210013879Abstract: A power module includes a power circuit which includes one or more power semiconductors; and a control circuit which supplies a gate signal to each of the one or more power semiconductors. The control circuit includes one or more gate drivers which generate the gate signal in accordance with a control signal and in which a side to which the control signal is input and a side on which the gate signal is generated are insulated, a control input circuit to which the control signal is input and which supplies the control signal to the one or more gate drivers, and a control output circuit which supplies the gate signal to each of the power semiconductors.Type: ApplicationFiled: July 4, 2020Publication date: January 14, 2021Inventors: HIROKI KANAI, TOMOTOSHI SATOH, KOICHIRO FUJITA, KENICHI TANAKA, HIROYUKI KOMEDA, NAOMICHI FUJII
-
Patent number: 10892748Abstract: A power module includes a power circuit which includes one or more power semiconductors; and a control circuit which supplies a gate signal to each of the one or more power semiconductors. The control circuit includes one or more gate drivers which generate the gate signal in accordance with a control signal and in which a side to which the control signal is input and a side on which the gate signal is generated are insulated, a control input circuit to which the control signal is input and which supplies the control signal to the one or more gate drivers, and a control output circuit which supplies the gate signal to each of the power semiconductors.Type: GrantFiled: July 4, 2020Date of Patent: January 12, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Hiroki Kanai, Tomotoshi Satoh, Koichiro Fujita, Kenichi Tanaka, Hiroyuki Komeda, Naomichi Fujii
-
Patent number: 10811350Abstract: A primary-side electrode and a secondary-side electrode of a power device are disposed so as to straddle plural separate primary and secondary wires in a first conductive layer, a second conductive layer includes plural separate primary and secondary wires, an insulating part is disposed in a first insulating layer in a region between the primary and secondary wires and directly below the power device, an intralayer insulating part is disposed in the second conductive layer in a region between the primary and secondary wires and directly below the power device, and a via that connects the primary wire in the first conductive layer and the primary wire in the second conductive layer and connects the secondary wire in the first conductive layer and the secondary wire in the second conductive layer is disposed in the first insulating layer directly below the primary-side and secondary-side electrodes of the power device.Type: GrantFiled: May 31, 2019Date of Patent: October 20, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Hiroki Kanai, Tomotoshi Satoh, Kenichi Tanaka
-
Power semiconductor module, electronic device, and method for controlling power semiconductor module
Patent number: 10756011Abstract: In a power semiconductor module, a first conductive layer including first to fourth electrodes are formed on one of principal surfaces of an insulating layer, and a conductive substrate functioning as a second conductive layer is formed on the other one of principal surfaces. Current paths are switched by controlling switching of a first transistor and a second transistor disposed on a surface of the first conductive layer thereby performing a power conversion. A capacitor is connected, in a region, between the first electrode and the second electrode. When a current flows in the region through the second conductive layer, a charging/discharging current occurs in the capacitor, which results in magnetic field cancellation.Type: GrantFiled: November 12, 2018Date of Patent: August 25, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Tomotoshi Satoh, Hiroyuki Komeda, Kenichi Tanaka, Koichiro Fujita -
Patent number: 10651143Abstract: Provided is an electrode like a protruding electrode that is self-standing on a substrate. A conductive paste (202) contains a conductive powder, an alcoholic liquid component, and no adhesives. The conductive powder contains conductive particles having a thickness of 0.05 ?m or more and 0.1 ?m or less and a representative length of 5 ?m or more and 10 ?m or less, the representative length being a maximum diameter in a plane perpendicular to the direction of the thickness. The weight percentage of the alcoholic liquid component relative to the conductive paste is 8% or more and 20% or less.Type: GrantFiled: April 28, 2017Date of Patent: May 12, 2020Assignees: SHARP KABUSHIKI KAISHA, OSAKA UNIVERSITYInventors: Tomotoshi Satoh, Hiroya Sato, Katsuaki Suganuma, Aiji Suetake, Shijo Nagao, Jinting Jiu, Seiichiro Kihara
-
Publication number: 20190371722Abstract: A primary-side electrode and a secondary-side electrode of a power device are disposed so as to straddle plural separate primary and secondary wires in a first conductive layer, a second conductive layer includes plural separate primary and secondary wires, an insulating part is disposed in a first insulating layer in a region between the primary and secondary wires and directly below the power device, an intralayer insulating part is disposed in the second conductive layer in a region between the primary and secondary wires and directly below the power device, and a via that connects the primary wire in the first conductive layer and the primary wire in the second conductive layer and connects the secondary wire in the first conductive layer and the secondary wire in the second conductive layer is disposed in the first insulating layer directly below the primary-side and secondary-side electrodes of the power device.Type: ApplicationFiled: May 31, 2019Publication date: December 5, 2019Inventors: HIROKI KANAI, TOMOTOSHI SATOH, KENICHI TANAKA
-
Publication number: 20190157229Abstract: Provided is an electrode like a protruding electrode that is self-standing on a substrate. A conductive paste (202) contains a conductive powder, an alcoholic liquid component, and no adhesives. The conductive powder contains conductive particles having a thickness of 0.05 ?m or more and 0.1 ?m or less and a representative length of 5 ?m or more and 10 ?m or less, the representative length being a maximum diameter in a plane perpendicular to the direction of the thickness. The weight percentage of the alcoholic liquid component relative to the conductive paste is 8% or more and 20% or less.Type: ApplicationFiled: April 28, 2017Publication date: May 23, 2019Applicants: Sharp Kabushiki Kaisha, Osaka UniversityInventors: Tomotoshi SATOH, Hiroya SATO, Katsuaki SUGANUMA, Aiji SUETAKE, Shijo NAGAO, Jinting JIU, Seiichiro KIHARA
-
Publication number: 20190157971Abstract: A power supply circuit includes a first switch that is a FET composed of a GaN-based semiconductor material and a second switch that is another FET composed of a GaN-based semiconductor material. The drain of the first switch is connected to an input voltage side, the source of the first switch is connected to the drain of the second switch and an output voltage side. An false-turn-on suppression circuit that hinders, when one of the first switch and the second switch is switched on, the other of the first switch and the second switch from being switched on is connected to the gate of the first switch and/or the gate of the second switch.Type: ApplicationFiled: November 13, 2018Publication date: May 23, 2019Inventors: KOICHIRO FUJITA, KENICHI TANAKA, TOMOTOSHI SATOH
-
Publication number: 20190148281Abstract: In a power semiconductor module, a first conductive layer including first to fourth electrodes are formed on one of principal surfaces of an insulating layer, and a conductive substrate functioning as a second conductive layer is formed on the other one of principal surfaces. Current paths are switched by controlling switching of a first transistor and a second transistor disposed on a surface of the first conductive layer thereby performing a power conversion. A capacitor is connected, in a region, between the first electrode and the second electrode. When a current flows in the region through the second conductive layer, a charging/discharging current occurs in the capacitor, which results in magnetic field cancellation.Type: ApplicationFiled: November 12, 2018Publication date: May 16, 2019Inventors: TOMOTOSHI SATOH, HIROYUKI KOMEDA, KENICHI TANAKA, KOICHIRO FUJITA
-
Publication number: 20180317317Abstract: A glass wired substrate includes a glass support substrate having first and second surfaces. A first circuit unit is arranged on the first surface. A second circuit unit is arranged on the second surface On the second circuit unit, a trimmed pattern comprising a plurality of slits is formed.Type: ApplicationFiled: September 27, 2016Publication date: November 1, 2018Applicant: SHARP KABUSHIKI KAISHAInventors: HIROYUKI NAKANISHI, TOMOTOSHI SATOH
-
Patent number: 9917011Abstract: A semiconductor wafer is provided with a substrate, a GaN type semiconductor film which is laminated on the substrate, a plurality of element regions which are provided on the GaN type semiconductor film, a dielectric film which is laminated on the GaN type semiconductor film, and a dicing region which has a dicing groove which is provided in a lattice form without passing through the dielectric film described above so as to partition the element regions described above. Then, an end on the element region side of the dicing groove is higher or lower than a central portion of the dicing groove in a width direction in a bottom surface of the dicing groove.Type: GrantFiled: April 30, 2015Date of Patent: March 13, 2018Assignee: Sharp Kabushiki KaishaInventors: Satoshi Morishita, Tadashi Yasui, Takao Kinoshita, Tomotoshi Satoh
-
Patent number: 9721838Abstract: A production method for a semiconductor element (10) includes: a semiconductor element forming step of forming the semiconductor element (10) including a dielectric film (3); a dicing region forming step of forming dicing regions (11) by removing the dielectric film (3) in partition regions that partition the semiconductor element (10); and a dicing step of dicing the dicing regions (11).Type: GrantFiled: October 24, 2014Date of Patent: August 1, 2017Assignee: Sharp Kabushiki KaishaInventors: Fumiaki Matsuura, Tomotoshi Satoh
-
Publication number: 20170062375Abstract: A GaN-based power device (1) includes a bonding pad portion (2) to which an aluminum wire (3) is bonded by ultrasonic bonding, and a second electrode (42) which is formed under the bonding pad (2). Ultrasonic vibration is applied such that an angle ? between a direction in which the ultrasonic vibration is applied to a wire and a length direction of the second electrode (42) is 0°???45°.Type: ApplicationFiled: February 4, 2015Publication date: March 2, 2017Applicant: Sharp Kabushiki KaishaInventors: Etsuko ISHIZUKA, Tomotoshi SATOH, Hiroyuki NAKANISHI
-
Publication number: 20170005001Abstract: A semiconductor wafer is provided with a substrate, a GaN type semiconductor film which is laminated on the substrate, a plurality of element regions which are provided on the GaN type semiconductor film, a dielectric film which is laminated on the GaN type semiconductor film, and a dicing region which has a dicing groove which is provided in a lattice form without passing through the dielectric film described above so as to partition the element regions described above. Then, an end on the element region side of the dicing groove is higher or lower than a central portion of the dicing groove in a width direction in a bottom surface of the dicing groove.Type: ApplicationFiled: April 30, 2015Publication date: January 5, 2017Applicant: SHARP KABUSHIKI KAISHAInventors: Satoshi MORISHITA, Tadashi YASUI, Takao KINOSHITA, Tomotoshi SATOH
-
Publication number: 20160268167Abstract: A production method for a semiconductor element (10) includes: a semiconductor element forming step of forming the semiconductor element (10) including a dielectric film (3); a dicing region forming step of forming dicing regions (11) by removing the dielectric film (3) in partition regions that partition the semiconductor element (10); and a dicing step of dicing the dicing regions (11).Type: ApplicationFiled: October 24, 2014Publication date: September 15, 2016Inventors: Fumiaki Matsuura, Tomotoshi Satoh
-
Publication number: 20160056131Abstract: A primary surface of a normally-off field-effect transistor (102) on which a source electrode (120) is formed and a first primary surface of a die pad (105) are in contact with each other, and the die pad (105) also serves as a source terminal of a semiconductor device (100). Accordingly, a semiconductor device capable of decreasing an inductance, which is a matter of great importance for an operation of a cascode connection circuit, and improving performance of circuit operation is provided.Type: ApplicationFiled: February 28, 2014Publication date: February 25, 2016Applicant: SHARP KABUSHIKI KAISHAInventors: Tomotoshi SATOH, Eiji OGINO, Naoyasu IKETANI, Satoshi MORISHITA
-
Publication number: 20100313930Abstract: All solar battery cells are in a matrix disposition. Each row of the matrix includes at least two cell groups, and each column of the matrix includes at least two cell groups.Type: ApplicationFiled: June 2, 2010Publication date: December 16, 2010Inventors: Masato Yokobayashi, Tomotoshi Satoh, Hiroyuki Nakanishi
-
Publication number: 20100294358Abstract: A semiconductor chip and an interposer are bonded by a conductive die bonding material. Between the semiconductor chip and the interposer, an application region in which the die bonding material resides and a region in which a sealing resin resides are provided. This allows adhesivity between the semiconductor chip and the interposer to be higher than that in conventional semiconductor packages, thereby causing no detachment at the adhesive interface. As a result, it becomes possible to improve electrical property and long-term reliability as compared to conventional semiconductor packages. Moreover, it is also possible to prevent the semiconductor chip from warping.Type: ApplicationFiled: May 19, 2010Publication date: November 25, 2010Inventors: Hiroyuki NAKANISHI, Masahiro Okita, Kohji Miyata, Tomotoshi Satoh, Etsuko Ishizuka, Masato Yokobayashi
-
Patent number: 7218559Abstract: First memory chips each have a memory cell as storage means for storing data and do not have a redundant memory cell as redundant storage means for repairing an erroneous bit in the memory cell. Furthermore, a logic minimal in degree is solely provided for operation on a control logic of a second memory chip. The second memory chip has a control logic for effecting memory control of the memory cells, the redundant memory cells, etc. and a redundant memory cell for repairing an error bit of the first memory chips. The memory device is structured by stacking the first and second memory chips.Type: GrantFiled: September 14, 2005Date of Patent: May 15, 2007Assignee: Sharp Kabushiki KaishaInventor: Tomotoshi Satoh
-
Publication number: 20070096332Abstract: An electronic component capable of being assembled into a module in the form of a stack of a plurality of layers is provided. Terminals of terminal groups (31 to 36) are formed so as to have rotational symmetry of a predetermined fold-number or have rotational symmetry and symmetry with respect to the plane containing a symmetric axis line. The terminals (A0 to A7, RFCG) of common connection terminal groups (32, 36) have connecting portions formed on the both surfaces in a stacking direction. Among the terminals of individual connection terminal groups (31, 33), a specific terminal CS; KEY has a connection portion formed at least on one of the both surfaces in the stacking direction while the remaining associated terminals NC; DMY have connection portions formed on the both surfaces in the stacking direction.Type: ApplicationFiled: May 28, 2004Publication date: May 3, 2007Inventors: Tomotoshi Satoh, Yoshihiko Nemoto, Kenji Takahashi, Yukiharu Akiyama